1=====================
2PHY Abstraction Layer
3=====================
4
5Purpose
6=======
7
8Most network devices consist of set of registers which provide an interface
9to a MAC layer, which communicates with the physical connection through a
10PHY.  The PHY concerns itself with negotiating link parameters with the link
11partner on the other side of the network connection (typically, an ethernet
12cable), and provides a register interface to allow drivers to determine what
13settings were chosen, and to configure what settings are allowed.
14
15While these devices are distinct from the network devices, and conform to a
16standard layout for the registers, it has been common practice to integrate
17the PHY management code with the network driver.  This has resulted in large
18amounts of redundant code.  Also, on embedded systems with multiple (and
19sometimes quite different) ethernet controllers connected to the same
20management bus, it is difficult to ensure safe use of the bus.
21
22Since the PHYs are devices, and the management busses through which they are
23accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
24In doing so, it has these goals:
25
26#. Increase code-reuse
27#. Increase overall code-maintainability
28#. Speed development time for new network drivers, and for new systems
29
30Basically, this layer is meant to provide an interface to PHY devices which
31allows network driver writers to write as little code as possible, while
32still providing a full feature set.
33
34The MDIO bus
35============
36
37Most network devices are connected to a PHY by means of a management bus.
38Different devices use different busses (though some share common interfaces).
39In order to take advantage of the PAL, each bus interface needs to be
40registered as a distinct device.
41
42#. read and write functions must be implemented. Their prototypes are::
43
44	int write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
45	int read(struct mii_bus *bus, int mii_id, int regnum);
46
47   mii_id is the address on the bus for the PHY, and regnum is the register
48   number.  These functions are guaranteed not to be called from interrupt
49   time, so it is safe for them to block, waiting for an interrupt to signal
50   the operation is complete
51
52#. A reset function is optional. This is used to return the bus to an
53   initialized state.
54
55#. A probe function is needed.  This function should set up anything the bus
56   driver needs, setup the mii_bus structure, and register with the PAL using
57   mdiobus_register.  Similarly, there's a remove function to undo all of
58   that (use mdiobus_unregister).
59
60#. Like any driver, the device_driver structure must be configured, and init
61   exit functions are used to register the driver.
62
63#. The bus must also be declared somewhere as a device, and registered.
64
65As an example for how one driver implemented an mdio bus driver, see
66drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file
67for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
68
69(RG)MII/electrical interface considerations
70===========================================
71
72The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
73electrical signal interface using a synchronous 125Mhz clock signal and several
74data lines. Due to this design decision, a 1.5ns to 2ns delay must be added
75between the clock line (RXC or TXC) and the data lines to let the PHY (clock
76sink) have a large enough setup and hold time to sample the data lines correctly. The
77PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
78the PHY driver and optionally the MAC driver, implement the required delay. The
79values of phy_interface_t must be understood from the perspective of the PHY
80device itself, leading to the following:
81
82* PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any
83  internal delay by itself, it assumes that either the Ethernet MAC (if capable)
84  or the PCB traces insert the correct 1.5-2ns delay
85
86* PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay
87  for the transmit data lines (TXD[3:0]) processed by the PHY device
88
89* PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay
90  for the receive data lines (RXD[3:0]) processed by the PHY device
91
92* PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for
93  both transmit AND receive data lines from/to the PHY device
94
95Whenever possible, use the PHY side RGMII delay for these reasons:
96
97* PHY devices may offer sub-nanosecond granularity in how they allow a
98  receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
99  precision may be required to account for differences in PCB trace lengths
100
101* PHY devices are typically qualified for a large range of applications
102  (industrial, medical, automotive...), and they provide a constant and
103  reliable delay across temperature/pressure/voltage ranges
104
105* PHY device drivers in PHYLIB being reusable by nature, being able to
106  configure correctly a specified delay enables more designs with similar delay
107  requirements to be operated correctly
108
109For cases where the PHY is not capable of providing this delay, but the
110Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
111should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be
112configured correctly in order to provide the required transmit and/or receive
113side delay from the perspective of the PHY device. Conversely, if the Ethernet
114MAC driver looks at the phy_interface_t value, for any other mode but
115PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
116disabled.
117
118In case neither the Ethernet MAC, nor the PHY are capable of providing the
119required delays, as defined per the RGMII standard, several options may be
120available:
121
122* Some SoCs may offer a pin pad/mux/controller capable of configuring a given
123  set of pins' strength, delays, and voltage; and it may be a suitable
124  option to insert the expected 2ns RGMII delay.
125
126* Modifying the PCB design to include a fixed delay (e.g: using a specifically
127  designed serpentine), which may not require software configuration at all.
128
129Common problems with RGMII delay mismatch
130-----------------------------------------
131
132When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
133will most likely result in the clock and data line signals to be unstable when
134the PHY or MAC take a snapshot of these signals to translate them into logical
1351 or 0 states and reconstruct the data being transmitted/received. Typical
136symptoms include:
137
138* Transmission/reception partially works, and there is frequent or occasional
139  packet loss observed
140
141* Ethernet MAC may report some or all packets ingressing with a FCS/CRC error,
142  or just discard them all
143
144* Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
145  (since there is enough setup/hold time in that case)
146
147Connecting to a PHY
148===================
149
150Sometime during startup, the network driver needs to establish a connection
151between the PHY device, and the network device.  At this time, the PHY's bus
152and drivers need to all have been loaded, so it is ready for the connection.
153At this point, there are several ways to connect to the PHY:
154
155#. The PAL handles everything, and only calls the network driver when
156   the link state changes, so it can react.
157
158#. The PAL handles everything except interrupts (usually because the
159   controller has the interrupt registers).
160
161#. The PAL handles everything, but checks in with the driver every second,
162   allowing the network driver to react first to any changes before the PAL
163   does.
164
165#. The PAL serves only as a library of functions, with the network device
166   manually calling functions to update status, and configure the PHY
167
168
169Letting the PHY Abstraction Layer do Everything
170===============================================
171
172If you choose option 1 (The hope is that every driver can, but to still be
173useful to drivers that can't), connecting to the PHY is simple:
174
175First, you need a function to react to changes in the link state.  This
176function follows this protocol::
177
178	static void adjust_link(struct net_device *dev);
179
180Next, you need to know the device name of the PHY connected to this device.
181The name will look something like, "0:00", where the first number is the
182bus id, and the second is the PHY's address on that bus.  Typically,
183the bus is responsible for making its ID unique.
184
185Now, to connect, just call this function::
186
187	phydev = phy_connect(dev, phy_name, &adjust_link, interface);
188
189*phydev* is a pointer to the phy_device structure which represents the PHY.
190If phy_connect is successful, it will return the pointer.  dev, here, is the
191pointer to your net_device.  Once done, this function will have started the
192PHY's software state machine, and registered for the PHY's interrupt, if it
193has one.  The phydev structure will be populated with information about the
194current state, though the PHY will not yet be truly operational at this
195point.
196
197PHY-specific flags should be set in phydev->dev_flags prior to the call
198to phy_connect() such that the underlying PHY driver can check for flags
199and perform specific operations based on them.
200This is useful if the system has put hardware restrictions on
201the PHY/controller, of which the PHY needs to be aware.
202
203*interface* is a u32 which specifies the connection type used
204between the controller and the PHY.  Examples are GMII, MII,
205RGMII, and SGMII.  See "PHY interface mode" below.  For a full
206list, see include/linux/phy.h
207
208Now just make sure that phydev->supported and phydev->advertising have any
209values pruned from them which don't make sense for your controller (a 10/100
210controller may be connected to a gigabit capable PHY, so you would need to
211mask off SUPPORTED_1000baseT*).  See include/linux/ethtool.h for definitions
212for these bitfields. Note that you should not SET any bits, except the
213SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get
214put into an unsupported state.
215
216Lastly, once the controller is ready to handle network traffic, you call
217phy_start(phydev).  This tells the PAL that you are ready, and configures the
218PHY to connect to the network. If the MAC interrupt of your network driver
219also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
220before you call phy_start and use phy_mac_interrupt() from the network
221driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
222phy_start() enables the PHY interrupts (if applicable) and starts the
223phylib state machine.
224
225When you want to disconnect from the network (even if just briefly), you call
226phy_stop(phydev). This function also stops the phylib state machine and
227disables PHY interrupts.
228
229PHY interface modes
230===================
231
232The PHY interface mode supplied in the phy_connect() family of functions
233defines the initial operating mode of the PHY interface.  This is not
234guaranteed to remain constant; there are PHYs which dynamically change
235their interface mode without software interaction depending on the
236negotiation results.
237
238Some of the interface modes are described below:
239
240``PHY_INTERFACE_MODE_SMII``
241    This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
242    Some details can be found in
243    https://opencores.org/ocsvn/smii/smii/trunk/doc/SMII.pdf
244
245``PHY_INTERFACE_MODE_1000BASEX``
246    This defines the 1000BASE-X single-lane serdes link as defined by the
247    802.3 standard section 36.  The link operates at a fixed bit rate of
248    1.25Gbaud using a 10B/8B encoding scheme, resulting in an underlying
249    data rate of 1Gbps.  Embedded in the data stream is a 16-bit control
250    word which is used to negotiate the duplex and pause modes with the
251    remote end.  This does not include "up-clocked" variants such as 2.5Gbps
252    speeds (see below.)
253
254``PHY_INTERFACE_MODE_2500BASEX``
255    This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
256    as the 802.3 standard, giving a fixed bit rate of 3.125Gbaud.
257
258``PHY_INTERFACE_MODE_SGMII``
259    This is used for Cisco SGMII, which is a modification of 1000BASE-X
260    as defined by the 802.3 standard.  The SGMII link consists of a single
261    serdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8B
262    encoding.  The underlying data rate is 1Gbps, with the slower speeds of
263    100Mbps and 10Mbps being achieved through replication of each data symbol.
264    The 802.3 control word is re-purposed to send the negotiated speed and
265    duplex information from to the MAC, and for the MAC to acknowledge
266    receipt.  This does not include "up-clocked" variants such as 2.5Gbps
267    speeds.
268
269    Note: mismatched SGMII vs 1000BASE-X configuration on a link can
270    successfully pass data in some circumstances, but the 16-bit control
271    word will not be correctly interpreted, which may cause mismatches in
272    duplex, pause or other settings.  This is dependent on the MAC and/or
273    PHY behaviour.
274
275``PHY_INTERFACE_MODE_5GBASER``
276    This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
277    identical to the 10GBASE-R protocol defined in Clause 49, with the
278    exception that it operates at half the frequency. Please refer to the
279    IEEE standard for the definition.
280
281``PHY_INTERFACE_MODE_10GBASER``
282    This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
283    various different mediums. Please refer to the IEEE standard for a
284    definition of this.
285
286    Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
287    XFI and SFI permit multiple protocols over a single SERDES lane, and
288    also defines the electrical characteristics of the signals with a host
289    compliance board plugged into the host XFP/SFP connector. Therefore,
290    XFI and SFI are not PHY interface types in their own right.
291
292``PHY_INTERFACE_MODE_10GKR``
293    This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
294    autonegotiation. Please refer to the IEEE standard for further
295    information.
296
297    Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
298    use of this definition.
299
300``PHY_INTERFACE_MODE_25GBASER``
301    This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302    The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
303    running 2.5 as fast, giving a fixed bit rate of 25.78125 Gbaud.
304    Please refer to the IEEE standard for further information.
305
306``PHY_INTERFACE_MODE_100BASEX``
307    This defines IEEE 802.3 Clause 24.  The link operates at a fixed data
308    rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
309    data rate of 100Mpbs.
310
311``PHY_INTERFACE_MODE_QUSGMII``
312    This defines the Cisco the Quad USGMII mode, which is the Quad variant of
313    the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses
314    a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
315    only the port id, but also so-called "extensions". The only documented
316    extension so-far in the specification is the inclusion of timestamps, for
317    PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
318    same capabilities in terms of link speed and negotiation.
319
320``PHY_INTERFACE_MODE_1000BASEKX``
321    This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
322    autonegotiation. Generally, it will be used with a Clause 70 PMD. To
323    contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
324    interface mode has different autonegotiation and only supports full duplex.
325
326``PHY_INTERFACE_MODE_PSGMII``
327    This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
328    SGMII lines into a single link compared to 4 on QSGMII.
329
330Pause frames / flow control
331===========================
332
333The PHY does not participate directly in flow control/pause frames except by
334making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
335MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
336controller supports such a thing. Since flow control/pause frames generation
337involves the Ethernet MAC driver, it is recommended that this driver takes care
338of properly indicating advertisement and support for such features by setting
339the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
340either before or after phy_connect() and/or as a result of implementing the
341ethtool::set_pauseparam feature.
342
343
344Keeping Close Tabs on the PAL
345=============================
346
347It is possible that the PAL's built-in state machine needs a little help to
348keep your network device and the PHY properly in sync.  If so, you can
349register a helper function when connecting to the PHY, which will be called
350every second before the state machine reacts to any changes.  To do this, you
351need to manually call phy_attach() and phy_prepare_link(), and then call
352phy_start_machine() with the second argument set to point to your special
353handler.
354
355Currently there are no examples of how to use this functionality, and testing
356on it has been limited because the author does not have any drivers which use
357it (they all use option 1).  So Caveat Emptor.
358
359Doing it all yourself
360=====================
361
362There's a remote chance that the PAL's built-in state machine cannot track
363the complex interactions between the PHY and your network device.  If this is
364so, you can simply call phy_attach(), and not call phy_start_machine or
365phy_prepare_link().  This will mean that phydev->state is entirely yours to
366handle (phy_start and phy_stop toggle between some of the states, so you
367might need to avoid them).
368
369An effort has been made to make sure that useful functionality can be
370accessed without the state-machine running, and most of these functions are
371descended from functions which did not interact with a complex state-machine.
372However, again, no effort has been made so far to test running without the
373state machine, so tryer beware.
374
375Here is a brief rundown of the functions::
376
377 int phy_read(struct phy_device *phydev, u16 regnum);
378 int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
379
380Simple read/write primitives.  They invoke the bus's read/write function
381pointers.
382::
383
384 void phy_print_status(struct phy_device *phydev);
385
386A convenience function to print out the PHY status neatly.
387::
388
389 void phy_request_interrupt(struct phy_device *phydev);
390
391Requests the IRQ for the PHY interrupts.
392::
393
394 struct phy_device * phy_attach(struct net_device *dev, const char *phy_id,
395		                phy_interface_t interface);
396
397Attaches a network device to a particular PHY, binding the PHY to a generic
398driver if none was found during bus initialization.
399::
400
401 int phy_start_aneg(struct phy_device *phydev);
402
403Using variables inside the phydev structure, either configures advertising
404and resets autonegotiation, or disables autonegotiation, and configures
405forced settings.
406::
407
408 static inline int phy_read_status(struct phy_device *phydev);
409
410Fills the phydev structure with up-to-date information about the current
411settings in the PHY.
412::
413
414 int phy_ethtool_ksettings_set(struct phy_device *phydev,
415                               const struct ethtool_link_ksettings *cmd);
416
417Ethtool convenience functions.
418::
419
420 int phy_mii_ioctl(struct phy_device *phydev,
421                   struct mii_ioctl_data *mii_data, int cmd);
422
423The MII ioctl.  Note that this function will completely screw up the state
424machine if you write registers like BMCR, BMSR, ADVERTISE, etc.  Best to
425use this only to write registers which are not standard, and don't set off
426a renegotiation.
427
428PHY Device Drivers
429==================
430
431With the PHY Abstraction Layer, adding support for new PHYs is
432quite easy. In some cases, no work is required at all! However,
433many PHYs require a little hand-holding to get up-and-running.
434
435Generic PHY driver
436------------------
437
438If the desired PHY doesn't have any errata, quirks, or special
439features you want to support, then it may be best to not add
440support, and let the PHY Abstraction Layer's Generic PHY Driver
441do all of the work.
442
443Writing a PHY driver
444--------------------
445
446If you do need to write a PHY driver, the first thing to do is
447make sure it can be matched with an appropriate PHY device.
448This is done during bus initialization by reading the device's
449UID (stored in registers 2 and 3), then comparing it to each
450driver's phy_id field by ANDing it with each driver's
451phy_id_mask field.  Also, it needs a name.  Here's an example::
452
453   static struct phy_driver dm9161_driver = {
454         .phy_id         = 0x0181b880,
455	 .name           = "Davicom DM9161E",
456	 .phy_id_mask    = 0x0ffffff0,
457	 ...
458   }
459
460Next, you need to specify what features (speed, duplex, autoneg,
461etc) your PHY device and driver support.  Most PHYs support
462PHY_BASIC_FEATURES, but you can look in include/mii.h for other
463features.
464
465Each driver consists of a number of function pointers, documented
466in include/linux/phy.h under the phy_driver structure.
467
468Of these, only config_aneg and read_status are required to be
469assigned by the driver code.  The rest are optional.  Also, it is
470preferred to use the generic phy driver's versions of these two
471functions if at all possible: genphy_read_status and
472genphy_config_aneg.  If this is not possible, it is likely that
473you only need to perform some actions before and after invoking
474these functions, and so your functions will wrap the generic
475ones.
476
477Feel free to look at the Marvell, Cicada, and Davicom drivers in
478drivers/net/phy/ for examples (the lxt and qsemi drivers have
479not been tested as of this writing).
480
481The PHY's MMD register accesses are handled by the PAL framework
482by default, but can be overridden by a specific PHY driver if
483required. This could be the case if a PHY was released for
484manufacturing before the MMD PHY register definitions were
485standardized by the IEEE. Most modern PHYs will be able to use
486the generic PAL framework for accessing the PHY's MMD registers.
487An example of such usage is for Energy Efficient Ethernet support,
488implemented in the PAL. This support uses the PAL to access MMD
489registers for EEE query and configuration if the PHY supports
490the IEEE standard access mechanisms, or can use the PHY's specific
491access interfaces if overridden by the specific PHY driver. See
492the Micrel driver in drivers/net/phy/ for an example of how this
493can be implemented.
494
495Board Fixups
496============
497
498Sometimes the specific interaction between the platform and the PHY requires
499special handling.  For instance, to change where the PHY's clock input is,
500or to add a delay to account for latency issues in the data path.  In order
501to support such contingencies, the PHY Layer allows platform code to register
502fixups to be run when the PHY is brought up (or subsequently reset).
503
504When the PHY Layer brings up a PHY it checks to see if there are any fixups
505registered for it, matching based on UID (contained in the PHY device's phy_id
506field) and the bus identifier (contained in phydev->dev.bus_id).  Both must
507match, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided as
508wildcards for the bus ID and UID, respectively.
509
510When a match is found, the PHY layer will invoke the run function associated
511with the fixup.  This function is passed a pointer to the phy_device of
512interest.  It should therefore only operate on that PHY.
513
514The platform code can either register the fixup using phy_register_fixup()::
515
516	int phy_register_fixup(const char *phy_id,
517		u32 phy_uid, u32 phy_uid_mask,
518		int (*run)(struct phy_device *));
519
520Or using one of the two stubs, phy_register_fixup_for_uid() and
521phy_register_fixup_for_id()::
522
523 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
524		int (*run)(struct phy_device *));
525 int phy_register_fixup_for_id(const char *phy_id,
526		int (*run)(struct phy_device *));
527
528The stubs set one of the two matching criteria, and set the other one to
529match anything.
530
531When phy_register_fixup() or \*_for_uid()/\*_for_id() is called at module load
532time, the module needs to unregister the fixup and free allocated memory when
533it's unloaded.
534
535Call one of following function before unloading module::
536
537 int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask);
538 int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
539 int phy_register_fixup_for_id(const char *phy_id);
540
541Standards
542=========
543
544IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two:
545http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf
546
547RGMII v1.3:
548http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf
549
550RGMII v2.0:
551http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf
552