1========================= 2NXP SJA1105 switch driver 3========================= 4 5Overview 6======== 7 8The NXP SJA1105 is a family of 6 devices: 9 10- SJA1105E: First generation, no TTEthernet 11- SJA1105T: First generation, TTEthernet 12- SJA1105P: Second generation, no TTEthernet, no SGMII 13- SJA1105Q: Second generation, TTEthernet, no SGMII 14- SJA1105R: Second generation, no TTEthernet, SGMII 15- SJA1105S: Second generation, TTEthernet, SGMII 16 17These are SPI-managed automotive switches, with all ports being gigabit 18capable, and supporting MII/RMII/RGMII and optionally SGMII on one port. 19 20Being automotive parts, their configuration interface is geared towards 21set-and-forget use, with minimal dynamic interaction at runtime. They 22require a static configuration to be composed by software and packed 23with CRC and table headers, and sent over SPI. 24 25The static configuration is composed of several configuration tables. Each 26table takes a number of entries. Some configuration tables can be (partially) 27reconfigured at runtime, some not. Some tables are mandatory, some not: 28 29============================= ================== ============================= 30Table Mandatory Reconfigurable 31============================= ================== ============================= 32Schedule no no 33Schedule entry points if Scheduling no 34VL Lookup no no 35VL Policing if VL Lookup no 36VL Forwarding if VL Lookup no 37L2 Lookup no no 38L2 Policing yes no 39VLAN Lookup yes yes 40L2 Forwarding yes partially (fully on P/Q/R/S) 41MAC Config yes partially (fully on P/Q/R/S) 42Schedule Params if Scheduling no 43Schedule Entry Points Params if Scheduling no 44VL Forwarding Params if VL Forwarding no 45L2 Lookup Params no partially (fully on P/Q/R/S) 46L2 Forwarding Params yes no 47Clock Sync Params no no 48AVB Params no no 49General Params yes partially 50Retagging no yes 51xMII Params yes no 52SGMII no yes 53============================= ================== ============================= 54 55 56Also the configuration is write-only (software cannot read it back from the 57switch except for very few exceptions). 58 59The driver creates a static configuration at probe time, and keeps it at 60all times in memory, as a shadow for the hardware state. When required to 61change a hardware setting, the static configuration is also updated. 62If that changed setting can be transmitted to the switch through the dynamic 63reconfiguration interface, it is; otherwise the switch is reset and 64reprogrammed with the updated static configuration. 65 66Traffic support 67=============== 68 69The switches do not have hardware support for DSA tags, except for "slow 70protocols" for switch control as STP and PTP. For these, the switches have two 71programmable filters for link-local destination MACs. 72These are used to trap BPDUs and PTP traffic to the master netdevice, and are 73further used to support STP and 1588 ordinary clock/boundary clock 74functionality. For frames trapped to the CPU, source port and switch ID 75information is encoded by the hardware into the frames. 76 77But by leveraging ``CONFIG_NET_DSA_TAG_8021Q`` (a software-defined DSA tagging 78format based on VLANs), general-purpose traffic termination through the network 79stack can be supported under certain circumstances. 80 81Depending on VLAN awareness state, the following operating modes are possible 82with the switch: 83 84- Mode 1 (VLAN-unaware): a port is in this mode when it is used as a standalone 85 net device, or when it is enslaved to a bridge with ``vlan_filtering=0``. 86- Mode 2 (fully VLAN-aware): a port is in this mode when it is enslaved to a 87 bridge with ``vlan_filtering=1``. Access to the entire VLAN range is given to 88 the user through ``bridge vlan`` commands, but general-purpose (anything 89 other than STP, PTP etc) traffic termination is not possible through the 90 switch net devices. The other packets can be still by user space processed 91 through the DSA master interface (similar to ``DSA_TAG_PROTO_NONE``). 92- Mode 3 (best-effort VLAN-aware): a port is in this mode when enslaved to a 93 bridge with ``vlan_filtering=1``, and the devlink property of its parent 94 switch named ``best_effort_vlan_filtering`` is set to ``true``. When 95 configured like this, the range of usable VIDs is reduced (0 to 1023 and 3072 96 to 4094), so is the number of usable VIDs (maximum of 7 non-pvid VLANs per 97 port*), and shared VLAN learning is performed (FDB lookup is done only by 98 DMAC, not also by VID). 99 100To summarize, in each mode, the following types of traffic are supported over 101the switch net devices: 102 103+-------------+-----------+--------------+------------+ 104| | Mode 1 | Mode 2 | Mode 3 | 105+=============+===========+==============+============+ 106| Regular | Yes | No | Yes | 107| traffic | | (use master) | | 108+-------------+-----------+--------------+------------+ 109| Management | Yes | Yes | Yes | 110| traffic | | | | 111| (BPDU, PTP) | | | | 112+-------------+-----------+--------------+------------+ 113 114To configure the switch to operate in Mode 3, the following steps can be 115followed:: 116 117 ip link add dev br0 type bridge 118 # swp2 operates in Mode 1 now 119 ip link set dev swp2 master br0 120 # swp2 temporarily moves to Mode 2 121 ip link set dev br0 type bridge vlan_filtering 1 122 [ 61.204770] sja1105 spi0.1: Reset switch and programmed static config. Reason: VLAN filtering 123 [ 61.239944] sja1105 spi0.1: Disabled switch tagging 124 # swp3 now operates in Mode 3 125 devlink dev param set spi/spi0.1 name best_effort_vlan_filtering value true cmode runtime 126 [ 64.682927] sja1105 spi0.1: Reset switch and programmed static config. Reason: VLAN filtering 127 [ 64.711925] sja1105 spi0.1: Enabled switch tagging 128 # Cannot use VLANs in range 1024-3071 while in Mode 3. 129 bridge vlan add dev swp2 vid 1025 untagged pvid 130 RTNETLINK answers: Operation not permitted 131 bridge vlan add dev swp2 vid 100 132 bridge vlan add dev swp2 vid 101 untagged 133 bridge vlan 134 port vlan ids 135 swp5 1 PVID Egress Untagged 136 137 swp2 1 PVID Egress Untagged 138 100 139 101 Egress Untagged 140 141 swp3 1 PVID Egress Untagged 142 143 swp4 1 PVID Egress Untagged 144 145 br0 1 PVID Egress Untagged 146 bridge vlan add dev swp2 vid 102 147 bridge vlan add dev swp2 vid 103 148 bridge vlan add dev swp2 vid 104 149 bridge vlan add dev swp2 vid 105 150 bridge vlan add dev swp2 vid 106 151 bridge vlan add dev swp2 vid 107 152 # Cannot use mode than 7 VLANs per port while in Mode 3. 153 [ 3885.216832] sja1105 spi0.1: No more free subvlans 154 155\* "maximum of 7 non-pvid VLANs per port": Decoding VLAN-tagged packets on the 156CPU in mode 3 is possible through VLAN retagging of packets that go from the 157switch to the CPU. In cross-chip topologies, the port that goes to the CPU 158might also go to other switches. In that case, those other switches will see 159only a retagged packet (which only has meaning for the CPU). So if they are 160interested in this VLAN, they need to apply retagging in the reverse direction, 161to recover the original value from it. This consumes extra hardware resources 162for this switch. There is a maximum of 32 entries in the Retagging Table of 163each switch device. 164 165As an example, consider this cross-chip topology:: 166 167 +-------------------------------------------------+ 168 | Host SoC | 169 | +-------------------------+ | 170 | | DSA master for embedded | | 171 | | switch (non-sja1105) | | 172 | +--------+-------------------------+--------+ | 173 | | embedded L2 switch | | 174 | | | | 175 | | +--------------+ +--------------+ | | 176 | | |DSA master for| |DSA master for| | | 177 | | | SJA1105 1 | | SJA1105 2 | | | 178 +--+---+--------------+-----+--------------+---+--+ 179 180 +-----------------------+ +-----------------------+ 181 | SJA1105 switch 1 | | SJA1105 switch 2 | 182 +-----+-----+-----+-----+ +-----+-----+-----+-----+ 183 |sw1p0|sw1p1|sw1p2|sw1p3| |sw2p0|sw2p1|sw2p2|sw2p3| 184 +-----+-----+-----+-----+ +-----+-----+-----+-----+ 185 186To reach the CPU, SJA1105 switch 1 (spi/spi2.1) uses the same port as is uses 187to reach SJA1105 switch 2 (spi/spi2.2), which would be port 4 (not drawn). 188Similarly for SJA1105 switch 2. 189 190Also consider the following commands, that add VLAN 100 to every sja1105 user 191port:: 192 193 devlink dev param set spi/spi2.1 name best_effort_vlan_filtering value true cmode runtime 194 devlink dev param set spi/spi2.2 name best_effort_vlan_filtering value true cmode runtime 195 ip link add dev br0 type bridge 196 for port in sw1p0 sw1p1 sw1p2 sw1p3 \ 197 sw2p0 sw2p1 sw2p2 sw2p3; do 198 ip link set dev $port master br0 199 done 200 ip link set dev br0 type bridge vlan_filtering 1 201 for port in sw1p0 sw1p1 sw1p2 sw1p3 \ 202 sw2p0 sw2p1 sw2p2; do 203 bridge vlan add dev $port vid 100 204 done 205 ip link add link br0 name br0.100 type vlan id 100 && ip link set dev br0.100 up 206 ip addr add 192.168.100.3/24 dev br0.100 207 bridge vlan add dev br0 vid 100 self 208 209 bridge vlan 210 port vlan ids 211 sw1p0 1 PVID Egress Untagged 212 100 213 214 sw1p1 1 PVID Egress Untagged 215 100 216 217 sw1p2 1 PVID Egress Untagged 218 100 219 220 sw1p3 1 PVID Egress Untagged 221 100 222 223 sw2p0 1 PVID Egress Untagged 224 100 225 226 sw2p1 1 PVID Egress Untagged 227 100 228 229 sw2p2 1 PVID Egress Untagged 230 100 231 232 sw2p3 1 PVID Egress Untagged 233 234 br0 1 PVID Egress Untagged 235 100 236 237SJA1105 switch 1 consumes 1 retagging entry for each VLAN on each user port 238towards the CPU. It also consumes 1 retagging entry for each non-pvid VLAN that 239it is also interested in, which is configured on any port of any neighbor 240switch. 241 242In this case, SJA1105 switch 1 consumes a total of 11 retagging entries, as 243follows: 244- 8 retagging entries for VLANs 1 and 100 installed on its user ports 245 (``sw1p0`` - ``sw1p3``) 246- 3 retagging entries for VLAN 100 installed on the user ports of SJA1105 247 switch 2 (``sw2p0`` - ``sw2p2``), because it also has ports that are 248 interested in it. The VLAN 1 is a pvid on SJA1105 switch 2 and does not need 249 reverse retagging. 250 251SJA1105 switch 2 also consumes 11 retagging entries, but organized as follows: 252- 7 retagging entries for the bridge VLANs on its user ports (``sw2p0`` - 253 ``sw2p3``). 254- 4 retagging entries for VLAN 100 installed on the user ports of SJA1105 255 switch 1 (``sw1p0`` - ``sw1p3``). 256 257Switching features 258================== 259 260The driver supports the configuration of L2 forwarding rules in hardware for 261port bridging. The forwarding, broadcast and flooding domain between ports can 262be restricted through two methods: either at the L2 forwarding level (isolate 263one bridge's ports from another's) or at the VLAN port membership level 264(isolate ports within the same bridge). The final forwarding decision taken by 265the hardware is a logical AND of these two sets of rules. 266 267The hardware tags all traffic internally with a port-based VLAN (pvid), or it 268decodes the VLAN information from the 802.1Q tag. Advanced VLAN classification 269is not possible. Once attributed a VLAN tag, frames are checked against the 270port's membership rules and dropped at ingress if they don't match any VLAN. 271This behavior is available when switch ports are enslaved to a bridge with 272``vlan_filtering 1``. 273 274Normally the hardware is not configurable with respect to VLAN awareness, but 275by changing what TPID the switch searches 802.1Q tags for, the semantics of a 276bridge with ``vlan_filtering 0`` can be kept (accept all traffic, tagged or 277untagged), and therefore this mode is also supported. 278 279Segregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but 280all bridges should have the same level of VLAN awareness (either both have 281``vlan_filtering`` 0, or both 1). Also an inevitable limitation of the fact 282that VLAN awareness is global at the switch level is that once a bridge with 283``vlan_filtering`` enslaves at least one switch port, the other un-bridged 284ports are no longer available for standalone traffic termination. 285 286Topology and loop detection through STP is supported. 287 288L2 FDB manipulation (add/delete/dump) is currently possible for the first 289generation devices. Aging time of FDB entries, as well as enabling fully static 290management (no address learning and no flooding of unknown traffic) is not yet 291configurable in the driver. 292 293A special comment about bridging with other netdevices (illustrated with an 294example): 295 296A board has eth0, eth1, swp0@eth1, swp1@eth1, swp2@eth1, swp3@eth1. 297The switch ports (swp0-3) are under br0. 298It is desired that eth0 is turned into another switched port that communicates 299with swp0-3. 300 301If br0 has vlan_filtering 0, then eth0 can simply be added to br0 with the 302intended results. 303If br0 has vlan_filtering 1, then a new br1 interface needs to be created that 304enslaves eth0 and eth1 (the DSA master of the switch ports). This is because in 305this mode, the switch ports beneath br0 are not capable of regular traffic, and 306are only used as a conduit for switchdev operations. 307 308Offloads 309======== 310 311Time-aware scheduling 312--------------------- 313 314The switch supports a variation of the enhancements for scheduled traffic 315specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to 316ensure deterministic latency for priority traffic that is sent in-band with its 317gate-open event in the network schedule. 318 319This capability can be managed through the tc-taprio offload ('flags 2'). The 320difference compared to the software implementation of taprio is that the latter 321would only be able to shape traffic originated from the CPU, but not 322autonomously forwarded flows. 323 324The device has 8 traffic classes, and maps incoming frames to one of them based 325on the VLAN PCP bits (if no VLAN is present, the port-based default is used). 326As described in the previous sections, depending on the value of 327``vlan_filtering``, the EtherType recognized by the switch as being VLAN can 328either be the typical 0x8100 or a custom value used internally by the driver 329for tagging. Therefore, the switch ignores the VLAN PCP if used in standalone 330or bridge mode with ``vlan_filtering=0``, as it will not recognize the 0x8100 331EtherType. In these modes, injecting into a particular TX queue can only be 332done by the DSA net devices, which populate the PCP field of the tagging header 333on egress. Using ``vlan_filtering=1``, the behavior is the other way around: 334offloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA 335net devices are no longer able to do that. To inject frames into a hardware TX 336queue with VLAN awareness active, it is necessary to create a VLAN 337sub-interface on the DSA master port, and send normal (0x8100) VLAN-tagged 338towards the switch, with the VLAN PCP bits set appropriately. 339 340Management traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the 341notable exception: the switch always treats it with a fixed priority and 342disregards any VLAN PCP bits even if present. The traffic class for management 343traffic has a value of 7 (highest priority) at the moment, which is not 344configurable in the driver. 345 346Below is an example of configuring a 500 us cyclic schedule on egress port 347``swp5``. The traffic class gate for management traffic (7) is open for 100 us, 348and the gates for all other traffic classes are open for 400 us:: 349 350 #!/bin/bash 351 352 set -e -u -o pipefail 353 354 NSEC_PER_SEC="1000000000" 355 356 gatemask() { 357 local tc_list="$1" 358 local mask=0 359 360 for tc in ${tc_list}; do 361 mask=$((${mask} | (1 << ${tc}))) 362 done 363 364 printf "%02x" ${mask} 365 } 366 367 if ! systemctl is-active --quiet ptp4l; then 368 echo "Please start the ptp4l service" 369 exit 370 fi 371 372 now=$(phc_ctl /dev/ptp1 get | gawk '/clock time is/ { print $5; }') 373 # Phase-align the base time to the start of the next second. 374 sec=$(echo "${now}" | gawk -F. '{ print $1; }') 375 base_time="$(((${sec} + 1) * ${NSEC_PER_SEC}))" 376 377 tc qdisc add dev swp5 parent root handle 100 taprio \ 378 num_tc 8 \ 379 map 0 1 2 3 5 6 7 \ 380 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ 381 base-time ${base_time} \ 382 sched-entry S $(gatemask 7) 100000 \ 383 sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \ 384 flags 2 385 386It is possible to apply the tc-taprio offload on multiple egress ports. There 387are hardware restrictions related to the fact that no gate event may trigger 388simultaneously on two ports. The driver checks the consistency of the schedules 389against this restriction and errors out when appropriate. Schedule analysis is 390needed to avoid this, which is outside the scope of the document. 391 392Routing actions (redirect, trap, drop) 393-------------------------------------- 394 395The switch is able to offload flow-based redirection of packets to a set of 396destination ports specified by the user. Internally, this is implemented by 397making use of Virtual Links, a TTEthernet concept. 398 399The driver supports 2 types of keys for Virtual Links: 400 401- VLAN-aware virtual links: these match on destination MAC address, VLAN ID and 402 VLAN PCP. 403- VLAN-unaware virtual links: these match on destination MAC address only. 404 405The VLAN awareness state of the bridge (vlan_filtering) cannot be changed while 406there are virtual link rules installed. 407 408Composing multiple actions inside the same rule is supported. When only routing 409actions are requested, the driver creates a "non-critical" virtual link. When 410the action list also contains tc-gate (more details below), the virtual link 411becomes "time-critical" (draws frame buffers from a reserved memory partition, 412etc). 413 414The 3 routing actions that are supported are "trap", "drop" and "redirect". 415 416Example 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the 417CPU and to swp3. This type of key (DA only) when the port's VLAN awareness 418state is off:: 419 420 tc qdisc add dev swp2 clsact 421 tc filter add dev swp2 ingress flower skip_sw dst_mac 42:be:24:9b:76:20 \ 422 action mirred egress redirect dev swp3 \ 423 action trap 424 425Example 2: drop frames received on swp2 with a DA of 42:be:24:9b:76:20, a VID 426of 100 and a PCP of 0:: 427 428 tc filter add dev swp2 ingress protocol 802.1Q flower skip_sw \ 429 dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop 430 431Time-based ingress policing 432--------------------------- 433 434The TTEthernet hardware abilities of the switch can be constrained to act 435similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in 436IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform 437tight timing-based admission control for up to 1024 flows (identified by a 438tuple composed of destination MAC address, VLAN ID and VLAN PCP). Packets which 439are received outside their expected reception window are dropped. 440 441This capability can be managed through the offload of the tc-gate action. As 442routing actions are intrinsic to virtual links in TTEthernet (which performs 443explicit routing of time-critical traffic and does not leave that in the hands 444of the FDB, flooding etc), the tc-gate action may never appear alone when 445asking sja1105 to offload it. One (or more) redirect or trap actions must also 446follow along. 447 448Example: create a tc-taprio schedule that is phase-aligned with a tc-gate 449schedule (the clocks must be synchronized by a 1588 application stack, which is 450outside the scope of this document). No packet delivered by the sender will be 451dropped. Note that the reception window is larger than the transmission window 452(and much more so, in this example) to compensate for the packet propagation 453delay of the link (which can be determined by the 1588 application stack). 454 455Receiver (sja1105):: 456 457 tc qdisc add dev swp2 clsact 458 now=$(phc_ctl /dev/ptp1 get | awk '/clock time is/ {print $5}') && \ 459 sec=$(echo $now | awk -F. '{print $1}') && \ 460 base_time="$(((sec + 2) * 1000000000))" && \ 461 echo "base time ${base_time}" 462 tc filter add dev swp2 ingress flower skip_sw \ 463 dst_mac 42:be:24:9b:76:20 \ 464 action gate base-time ${base_time} \ 465 sched-entry OPEN 60000 -1 -1 \ 466 sched-entry CLOSE 40000 -1 -1 \ 467 action trap 468 469Sender:: 470 471 now=$(phc_ctl /dev/ptp0 get | awk '/clock time is/ {print $5}') && \ 472 sec=$(echo $now | awk -F. '{print $1}') && \ 473 base_time="$(((sec + 2) * 1000000000))" && \ 474 echo "base time ${base_time}" 475 tc qdisc add dev eno0 parent root taprio \ 476 num_tc 8 \ 477 map 0 1 2 3 4 5 6 7 \ 478 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ 479 base-time ${base_time} \ 480 sched-entry S 01 50000 \ 481 sched-entry S 00 50000 \ 482 flags 2 483 484The engine used to schedule the ingress gate operations is the same that the 485one used for the tc-taprio offload. Therefore, the restrictions regarding the 486fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at 487the same time (during the same 200 ns slot) still apply. 488 489To come in handy, it is possible to share time-triggered virtual links across 490more than 1 ingress port, via flow blocks. In this case, the restriction of 491firing at the same time does not apply because there is a single schedule in 492the system, that of the shared virtual link:: 493 494 tc qdisc add dev swp2 ingress_block 1 clsact 495 tc qdisc add dev swp3 ingress_block 1 clsact 496 tc filter add block 1 flower skip_sw dst_mac 42:be:24:9b:76:20 \ 497 action gate index 2 \ 498 base-time 0 \ 499 sched-entry OPEN 50000000 -1 -1 \ 500 sched-entry CLOSE 50000000 -1 -1 \ 501 action trap 502 503Hardware statistics for each flow are also available ("pkts" counts the number 504of dropped frames, which is a sum of frames dropped due to timing violations, 505lack of destination ports and MTU enforcement checks). Byte-level counters are 506not available. 507 508Device Tree bindings and board design 509===================================== 510 511This section references ``Documentation/devicetree/bindings/net/dsa/sja1105.txt`` 512and aims to showcase some potential switch caveats. 513 514RMII PHY role and out-of-band signaling 515--------------------------------------- 516 517In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by 518an external oscillator (but not by the PHY). 519But the spec is rather loose and devices go outside it in several ways. 520Some PHYs go against the spec and may provide an output pin where they source 521the 50 MHz clock themselves, in an attempt to be helpful. 522On the other hand, the SJA1105 is only binary configurable - when in the RMII 523MAC role it will also attempt to drive the clock signal. To prevent this from 524happening it must be put in RMII PHY role. 525But doing so has some unintended consequences. 526In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0]. 527These are practically some extra code words (/J/ and /K/) sent prior to the 528preamble of each frame. The MAC does not have this out-of-band signaling 529mechanism defined by the RMII spec. 530So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the 531clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105 532emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to 533frame preambles, which the real PHY is not expected to understand. So the PHY 534simply encodes the extra symbols received from the SJA1105-as-PHY onto the 535100Base-Tx wire. 536On the other side of the wire, some link partners might discard these extra 537symbols, while others might choke on them and discard the entire Ethernet 538frames that follow along. This looks like packet loss with some link partners 539but not with others. 540The take-away is that in RMII mode, the SJA1105 must be let to drive the 541reference clock if connected to a PHY. 542 543RGMII fixed-link and internal delays 544------------------------------------ 545 546As mentioned in the bindings document, the second generation of devices has 547tunable delay lines as part of the MAC, which can be used to establish the 548correct RGMII timing budget. 549When powered up, these can shift the Rx and Tx clocks with a phase difference 550between 73.8 and 101.7 degrees. 551The catch is that the delay lines need to lock onto a clock signal with a 552stable frequency. This means that there must be at least 2 microseconds of 553silence between the clock at the old vs at the new frequency. Otherwise the 554lock is lost and the delay lines must be reset (powered down and back up). 555In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25 556MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the 557AN process. 558In the situation where the switch port is connected through an RGMII fixed-link 559to a link partner whose link state life cycle is outside the control of Linux 560(such as a different SoC), then the delay lines would remain unlocked (and 561inactive) until there is manual intervention (ifdown/ifup on the switch port). 562The take-away is that in RGMII mode, the switch's internal delays are only 563reliable if the link partner never changes link speeds, or if it does, it does 564so in a way that is coordinated with the switch port (practically, both ends of 565the fixed-link are under control of the same Linux system). 566As to why would a fixed-link interface ever change link speeds: there are 567Ethernet controllers out there which come out of reset in 100 Mbps mode, and 568their driver inevitably needs to change the speed and clock frequency if it's 569required to work at gigabit. 570 571MDIO bus and PHY management 572--------------------------- 573 574The SJA1105 does not have an MDIO bus and does not perform in-band AN either. 575Therefore there is no link state notification coming from the switch device. 576A board would need to hook up the PHYs connected to the switch to any other 577MDIO bus available to Linux within the system (e.g. to the DSA master's MDIO 578bus). Link state management then works by the driver manually keeping in sync 579(over SPI commands) the MAC link speed with the settings negotiated by the PHY. 580