1 ============================ 2 LINUX KERNEL MEMORY BARRIERS 3 ============================ 4 5By: David Howells <dhowells@redhat.com> 6 Paul E. McKenney <paulmck@linux.vnet.ibm.com> 7 8Contents: 9 10 (*) Abstract memory access model. 11 12 - Device operations. 13 - Guarantees. 14 15 (*) What are memory barriers? 16 17 - Varieties of memory barrier. 18 - What may not be assumed about memory barriers? 19 - Data dependency barriers. 20 - Control dependencies. 21 - SMP barrier pairing. 22 - Examples of memory barrier sequences. 23 - Read memory barriers vs load speculation. 24 - Transitivity 25 26 (*) Explicit kernel barriers. 27 28 - Compiler barrier. 29 - CPU memory barriers. 30 - MMIO write barrier. 31 32 (*) Implicit kernel memory barriers. 33 34 - Locking functions. 35 - Interrupt disabling functions. 36 - Sleep and wake-up functions. 37 - Miscellaneous functions. 38 39 (*) Inter-CPU locking barrier effects. 40 41 - Locks vs memory accesses. 42 - Locks vs I/O accesses. 43 44 (*) Where are memory barriers needed? 45 46 - Interprocessor interaction. 47 - Atomic operations. 48 - Accessing devices. 49 - Interrupts. 50 51 (*) Kernel I/O barrier effects. 52 53 (*) Assumed minimum execution ordering model. 54 55 (*) The effects of the cpu cache. 56 57 - Cache coherency. 58 - Cache coherency vs DMA. 59 - Cache coherency vs MMIO. 60 61 (*) The things CPUs get up to. 62 63 - And then there's the Alpha. 64 65 (*) Example uses. 66 67 - Circular buffers. 68 69 (*) References. 70 71 72============================ 73ABSTRACT MEMORY ACCESS MODEL 74============================ 75 76Consider the following abstract model of the system: 77 78 : : 79 : : 80 : : 81 +-------+ : +--------+ : +-------+ 82 | | : | | : | | 83 | | : | | : | | 84 | CPU 1 |<----->| Memory |<----->| CPU 2 | 85 | | : | | : | | 86 | | : | | : | | 87 +-------+ : +--------+ : +-------+ 88 ^ : ^ : ^ 89 | : | : | 90 | : | : | 91 | : v : | 92 | : +--------+ : | 93 | : | | : | 94 | : | | : | 95 +---------->| Device |<----------+ 96 : | | : 97 : | | : 98 : +--------+ : 99 : : 100 101Each CPU executes a program that generates memory access operations. In the 102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually 103perform the memory operations in any order it likes, provided program causality 104appears to be maintained. Similarly, the compiler may also arrange the 105instructions it emits in any order it likes, provided it doesn't affect the 106apparent operation of the program. 107 108So in the above diagram, the effects of the memory operations performed by a 109CPU are perceived by the rest of the system as the operations cross the 110interface between the CPU and rest of the system (the dotted lines). 111 112 113For example, consider the following sequence of events: 114 115 CPU 1 CPU 2 116 =============== =============== 117 { A == 1; B == 2 } 118 A = 3; x = A; 119 B = 4; y = B; 120 121The set of accesses as seen by the memory system in the middle can be arranged 122in 24 different combinations: 123 124 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4 125 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3 126 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4 127 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4 128 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3 129 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4 130 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4 131 STORE B=4, ... 132 ... 133 134and can thus result in four different combinations of values: 135 136 x == 1, y == 2 137 x == 1, y == 4 138 x == 3, y == 2 139 x == 3, y == 4 140 141 142Furthermore, the stores committed by a CPU to the memory system may not be 143perceived by the loads made by another CPU in the same order as the stores were 144committed. 145 146 147As a further example, consider this sequence of events: 148 149 CPU 1 CPU 2 150 =============== =============== 151 { A == 1, B == 2, C = 3, P == &A, Q == &C } 152 B = 4; Q = P; 153 P = &B D = *Q; 154 155There is an obvious data dependency here, as the value loaded into D depends on 156the address retrieved from P by CPU 2. At the end of the sequence, any of the 157following results are possible: 158 159 (Q == &A) and (D == 1) 160 (Q == &B) and (D == 2) 161 (Q == &B) and (D == 4) 162 163Note that CPU 2 will never try and load C into D because the CPU will load P 164into Q before issuing the load of *Q. 165 166 167DEVICE OPERATIONS 168----------------- 169 170Some devices present their control interfaces as collections of memory 171locations, but the order in which the control registers are accessed is very 172important. For instance, imagine an ethernet card with a set of internal 173registers that are accessed through an address port register (A) and a data 174port register (D). To read internal register 5, the following code might then 175be used: 176 177 *A = 5; 178 x = *D; 179 180but this might show up as either of the following two sequences: 181 182 STORE *A = 5, x = LOAD *D 183 x = LOAD *D, STORE *A = 5 184 185the second of which will almost certainly result in a malfunction, since it set 186the address _after_ attempting to read the register. 187 188 189GUARANTEES 190---------- 191 192There are some minimal guarantees that may be expected of a CPU: 193 194 (*) On any given CPU, dependent memory accesses will be issued in order, with 195 respect to itself. This means that for: 196 197 Q = P; D = *Q; 198 199 the CPU will issue the following memory operations: 200 201 Q = LOAD P, D = LOAD *Q 202 203 and always in that order. 204 205 (*) Overlapping loads and stores within a particular CPU will appear to be 206 ordered within that CPU. This means that for: 207 208 a = *X; *X = b; 209 210 the CPU will only issue the following sequence of memory operations: 211 212 a = LOAD *X, STORE *X = b 213 214 And for: 215 216 *X = c; d = *X; 217 218 the CPU will only issue: 219 220 STORE *X = c, d = LOAD *X 221 222 (Loads and stores overlap if they are targeted at overlapping pieces of 223 memory). 224 225And there are a number of things that _must_ or _must_not_ be assumed: 226 227 (*) It _must_not_ be assumed that independent loads and stores will be issued 228 in the order given. This means that for: 229 230 X = *A; Y = *B; *D = Z; 231 232 we may get any of the following sequences: 233 234 X = LOAD *A, Y = LOAD *B, STORE *D = Z 235 X = LOAD *A, STORE *D = Z, Y = LOAD *B 236 Y = LOAD *B, X = LOAD *A, STORE *D = Z 237 Y = LOAD *B, STORE *D = Z, X = LOAD *A 238 STORE *D = Z, X = LOAD *A, Y = LOAD *B 239 STORE *D = Z, Y = LOAD *B, X = LOAD *A 240 241 (*) It _must_ be assumed that overlapping memory accesses may be merged or 242 discarded. This means that for: 243 244 X = *A; Y = *(A + 4); 245 246 we may get any one of the following sequences: 247 248 X = LOAD *A; Y = LOAD *(A + 4); 249 Y = LOAD *(A + 4); X = LOAD *A; 250 {X, Y} = LOAD {*A, *(A + 4) }; 251 252 And for: 253 254 *A = X; Y = *A; 255 256 we may get either of: 257 258 STORE *A = X; Y = LOAD *A; 259 STORE *A = Y = X; 260 261 262========================= 263WHAT ARE MEMORY BARRIERS? 264========================= 265 266As can be seen above, independent memory operations are effectively performed 267in random order, but this can be a problem for CPU-CPU interaction and for I/O. 268What is required is some way of intervening to instruct the compiler and the 269CPU to restrict the order. 270 271Memory barriers are such interventions. They impose a perceived partial 272ordering over the memory operations on either side of the barrier. 273 274Such enforcement is important because the CPUs and other devices in a system 275can use a variety of tricks to improve performance, including reordering, 276deferral and combination of memory operations; speculative loads; speculative 277branch prediction and various types of caching. Memory barriers are used to 278override or suppress these tricks, allowing the code to sanely control the 279interaction of multiple CPUs and/or devices. 280 281 282VARIETIES OF MEMORY BARRIER 283--------------------------- 284 285Memory barriers come in four basic varieties: 286 287 (1) Write (or store) memory barriers. 288 289 A write memory barrier gives a guarantee that all the STORE operations 290 specified before the barrier will appear to happen before all the STORE 291 operations specified after the barrier with respect to the other 292 components of the system. 293 294 A write barrier is a partial ordering on stores only; it is not required 295 to have any effect on loads. 296 297 A CPU can be viewed as committing a sequence of store operations to the 298 memory system as time progresses. All stores before a write barrier will 299 occur in the sequence _before_ all the stores after the write barrier. 300 301 [!] Note that write barriers should normally be paired with read or data 302 dependency barriers; see the "SMP barrier pairing" subsection. 303 304 305 (2) Data dependency barriers. 306 307 A data dependency barrier is a weaker form of read barrier. In the case 308 where two loads are performed such that the second depends on the result 309 of the first (eg: the first load retrieves the address to which the second 310 load will be directed), a data dependency barrier would be required to 311 make sure that the target of the second load is updated before the address 312 obtained by the first load is accessed. 313 314 A data dependency barrier is a partial ordering on interdependent loads 315 only; it is not required to have any effect on stores, independent loads 316 or overlapping loads. 317 318 As mentioned in (1), the other CPUs in the system can be viewed as 319 committing sequences of stores to the memory system that the CPU being 320 considered can then perceive. A data dependency barrier issued by the CPU 321 under consideration guarantees that for any load preceding it, if that 322 load touches one of a sequence of stores from another CPU, then by the 323 time the barrier completes, the effects of all the stores prior to that 324 touched by the load will be perceptible to any loads issued after the data 325 dependency barrier. 326 327 See the "Examples of memory barrier sequences" subsection for diagrams 328 showing the ordering constraints. 329 330 [!] Note that the first load really has to have a _data_ dependency and 331 not a control dependency. If the address for the second load is dependent 332 on the first load, but the dependency is through a conditional rather than 333 actually loading the address itself, then it's a _control_ dependency and 334 a full read barrier or better is required. See the "Control dependencies" 335 subsection for more information. 336 337 [!] Note that data dependency barriers should normally be paired with 338 write barriers; see the "SMP barrier pairing" subsection. 339 340 341 (3) Read (or load) memory barriers. 342 343 A read barrier is a data dependency barrier plus a guarantee that all the 344 LOAD operations specified before the barrier will appear to happen before 345 all the LOAD operations specified after the barrier with respect to the 346 other components of the system. 347 348 A read barrier is a partial ordering on loads only; it is not required to 349 have any effect on stores. 350 351 Read memory barriers imply data dependency barriers, and so can substitute 352 for them. 353 354 [!] Note that read barriers should normally be paired with write barriers; 355 see the "SMP barrier pairing" subsection. 356 357 358 (4) General memory barriers. 359 360 A general memory barrier gives a guarantee that all the LOAD and STORE 361 operations specified before the barrier will appear to happen before all 362 the LOAD and STORE operations specified after the barrier with respect to 363 the other components of the system. 364 365 A general memory barrier is a partial ordering over both loads and stores. 366 367 General memory barriers imply both read and write memory barriers, and so 368 can substitute for either. 369 370 371And a couple of implicit varieties: 372 373 (5) LOCK operations. 374 375 This acts as a one-way permeable barrier. It guarantees that all memory 376 operations after the LOCK operation will appear to happen after the LOCK 377 operation with respect to the other components of the system. 378 379 Memory operations that occur before a LOCK operation may appear to happen 380 after it completes. 381 382 A LOCK operation should almost always be paired with an UNLOCK operation. 383 384 385 (6) UNLOCK operations. 386 387 This also acts as a one-way permeable barrier. It guarantees that all 388 memory operations before the UNLOCK operation will appear to happen before 389 the UNLOCK operation with respect to the other components of the system. 390 391 Memory operations that occur after an UNLOCK operation may appear to 392 happen before it completes. 393 394 LOCK and UNLOCK operations are guaranteed to appear with respect to each 395 other strictly in the order specified. 396 397 The use of LOCK and UNLOCK operations generally precludes the need for 398 other sorts of memory barrier (but note the exceptions mentioned in the 399 subsection "MMIO write barrier"). 400 401 402Memory barriers are only required where there's a possibility of interaction 403between two CPUs or between a CPU and a device. If it can be guaranteed that 404there won't be any such interaction in any particular piece of code, then 405memory barriers are unnecessary in that piece of code. 406 407 408Note that these are the _minimum_ guarantees. Different architectures may give 409more substantial guarantees, but they may _not_ be relied upon outside of arch 410specific code. 411 412 413WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS? 414---------------------------------------------- 415 416There are certain things that the Linux kernel memory barriers do not guarantee: 417 418 (*) There is no guarantee that any of the memory accesses specified before a 419 memory barrier will be _complete_ by the completion of a memory barrier 420 instruction; the barrier can be considered to draw a line in that CPU's 421 access queue that accesses of the appropriate type may not cross. 422 423 (*) There is no guarantee that issuing a memory barrier on one CPU will have 424 any direct effect on another CPU or any other hardware in the system. The 425 indirect effect will be the order in which the second CPU sees the effects 426 of the first CPU's accesses occur, but see the next point: 427 428 (*) There is no guarantee that a CPU will see the correct order of effects 429 from a second CPU's accesses, even _if_ the second CPU uses a memory 430 barrier, unless the first CPU _also_ uses a matching memory barrier (see 431 the subsection on "SMP Barrier Pairing"). 432 433 (*) There is no guarantee that some intervening piece of off-the-CPU 434 hardware[*] will not reorder the memory accesses. CPU cache coherency 435 mechanisms should propagate the indirect effects of a memory barrier 436 between CPUs, but might not do so in order. 437 438 [*] For information on bus mastering DMA and coherency please read: 439 440 Documentation/PCI/pci.txt 441 Documentation/DMA-API-HOWTO.txt 442 Documentation/DMA-API.txt 443 444 445DATA DEPENDENCY BARRIERS 446------------------------ 447 448The usage requirements of data dependency barriers are a little subtle, and 449it's not always obvious that they're needed. To illustrate, consider the 450following sequence of events: 451 452 CPU 1 CPU 2 453 =============== =============== 454 { A == 1, B == 2, C = 3, P == &A, Q == &C } 455 B = 4; 456 <write barrier> 457 P = &B 458 Q = P; 459 D = *Q; 460 461There's a clear data dependency here, and it would seem that by the end of the 462sequence, Q must be either &A or &B, and that: 463 464 (Q == &A) implies (D == 1) 465 (Q == &B) implies (D == 4) 466 467But! CPU 2's perception of P may be updated _before_ its perception of B, thus 468leading to the following situation: 469 470 (Q == &B) and (D == 2) ???? 471 472Whilst this may seem like a failure of coherency or causality maintenance, it 473isn't, and this behaviour can be observed on certain real CPUs (such as the DEC 474Alpha). 475 476To deal with this, a data dependency barrier or better must be inserted 477between the address load and the data load: 478 479 CPU 1 CPU 2 480 =============== =============== 481 { A == 1, B == 2, C = 3, P == &A, Q == &C } 482 B = 4; 483 <write barrier> 484 P = &B 485 Q = P; 486 <data dependency barrier> 487 D = *Q; 488 489This enforces the occurrence of one of the two implications, and prevents the 490third possibility from arising. 491 492[!] Note that this extremely counterintuitive situation arises most easily on 493machines with split caches, so that, for example, one cache bank processes 494even-numbered cache lines and the other bank processes odd-numbered cache 495lines. The pointer P might be stored in an odd-numbered cache line, and the 496variable B might be stored in an even-numbered cache line. Then, if the 497even-numbered bank of the reading CPU's cache is extremely busy while the 498odd-numbered bank is idle, one can see the new value of the pointer P (&B), 499but the old value of the variable B (2). 500 501 502Another example of where data dependency barriers might by required is where a 503number is read from memory and then used to calculate the index for an array 504access: 505 506 CPU 1 CPU 2 507 =============== =============== 508 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 } 509 M[1] = 4; 510 <write barrier> 511 P = 1 512 Q = P; 513 <data dependency barrier> 514 D = M[Q]; 515 516 517The data dependency barrier is very important to the RCU system, for example. 518See rcu_dereference() in include/linux/rcupdate.h. This permits the current 519target of an RCU'd pointer to be replaced with a new modified target, without 520the replacement target appearing to be incompletely initialised. 521 522See also the subsection on "Cache Coherency" for a more thorough example. 523 524 525CONTROL DEPENDENCIES 526-------------------- 527 528A control dependency requires a full read memory barrier, not simply a data 529dependency barrier to make it work correctly. Consider the following bit of 530code: 531 532 q = &a; 533 if (p) 534 q = &b; 535 <data dependency barrier> 536 x = *q; 537 538This will not have the desired effect because there is no actual data 539dependency, but rather a control dependency that the CPU may short-circuit by 540attempting to predict the outcome in advance. In such a case what's actually 541required is: 542 543 q = &a; 544 if (p) 545 q = &b; 546 <read barrier> 547 x = *q; 548 549 550SMP BARRIER PAIRING 551------------------- 552 553When dealing with CPU-CPU interactions, certain types of memory barrier should 554always be paired. A lack of appropriate pairing is almost certainly an error. 555 556A write barrier should always be paired with a data dependency barrier or read 557barrier, though a general barrier would also be viable. Similarly a read 558barrier or a data dependency barrier should always be paired with at least an 559write barrier, though, again, a general barrier is viable: 560 561 CPU 1 CPU 2 562 =============== =============== 563 a = 1; 564 <write barrier> 565 b = 2; x = b; 566 <read barrier> 567 y = a; 568 569Or: 570 571 CPU 1 CPU 2 572 =============== =============================== 573 a = 1; 574 <write barrier> 575 b = &a; x = b; 576 <data dependency barrier> 577 y = *x; 578 579Basically, the read barrier always has to be there, even though it can be of 580the "weaker" type. 581 582[!] Note that the stores before the write barrier would normally be expected to 583match the loads after the read barrier or the data dependency barrier, and vice 584versa: 585 586 CPU 1 CPU 2 587 =============== =============== 588 a = 1; }---- --->{ v = c 589 b = 2; } \ / { w = d 590 <write barrier> \ <read barrier> 591 c = 3; } / \ { x = a; 592 d = 4; }---- --->{ y = b; 593 594 595EXAMPLES OF MEMORY BARRIER SEQUENCES 596------------------------------------ 597 598Firstly, write barriers act as partial orderings on store operations. 599Consider the following sequence of events: 600 601 CPU 1 602 ======================= 603 STORE A = 1 604 STORE B = 2 605 STORE C = 3 606 <write barrier> 607 STORE D = 4 608 STORE E = 5 609 610This sequence of events is committed to the memory coherence system in an order 611that the rest of the system might perceive as the unordered set of { STORE A, 612STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E 613}: 614 615 +-------+ : : 616 | | +------+ 617 | |------>| C=3 | } /\ 618 | | : +------+ }----- \ -----> Events perceptible to 619 | | : | A=1 | } \/ the rest of the system 620 | | : +------+ } 621 | CPU 1 | : | B=2 | } 622 | | +------+ } 623 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier 624 | | +------+ } requires all stores prior to the 625 | | : | E=5 | } barrier to be committed before 626 | | : +------+ } further stores may take place 627 | |------>| D=4 | } 628 | | +------+ 629 +-------+ : : 630 | 631 | Sequence in which stores are committed to the 632 | memory system by CPU 1 633 V 634 635 636Secondly, data dependency barriers act as partial orderings on data-dependent 637loads. Consider the following sequence of events: 638 639 CPU 1 CPU 2 640 ======================= ======================= 641 { B = 7; X = 9; Y = 8; C = &Y } 642 STORE A = 1 643 STORE B = 2 644 <write barrier> 645 STORE C = &B LOAD X 646 STORE D = 4 LOAD C (gets &B) 647 LOAD *C (reads B) 648 649Without intervention, CPU 2 may perceive the events on CPU 1 in some 650effectively random order, despite the write barrier issued by CPU 1: 651 652 +-------+ : : : : 653 | | +------+ +-------+ | Sequence of update 654 | |------>| B=2 |----- --->| Y->8 | | of perception on 655 | | : +------+ \ +-------+ | CPU 2 656 | CPU 1 | : | A=1 | \ --->| C->&Y | V 657 | | +------+ | +-------+ 658 | | wwwwwwwwwwwwwwww | : : 659 | | +------+ | : : 660 | | : | C=&B |--- | : : +-------+ 661 | | : +------+ \ | +-------+ | | 662 | |------>| D=4 | ----------->| C->&B |------>| | 663 | | +------+ | +-------+ | | 664 +-------+ : : | : : | | 665 | : : | | 666 | : : | CPU 2 | 667 | +-------+ | | 668 Apparently incorrect ---> | | B->7 |------>| | 669 perception of B (!) | +-------+ | | 670 | : : | | 671 | +-------+ | | 672 The load of X holds ---> \ | X->9 |------>| | 673 up the maintenance \ +-------+ | | 674 of coherence of B ----->| B->2 | +-------+ 675 +-------+ 676 : : 677 678 679In the above example, CPU 2 perceives that B is 7, despite the load of *C 680(which would be B) coming after the LOAD of C. 681 682If, however, a data dependency barrier were to be placed between the load of C 683and the load of *C (ie: B) on CPU 2: 684 685 CPU 1 CPU 2 686 ======================= ======================= 687 { B = 7; X = 9; Y = 8; C = &Y } 688 STORE A = 1 689 STORE B = 2 690 <write barrier> 691 STORE C = &B LOAD X 692 STORE D = 4 LOAD C (gets &B) 693 <data dependency barrier> 694 LOAD *C (reads B) 695 696then the following will occur: 697 698 +-------+ : : : : 699 | | +------+ +-------+ 700 | |------>| B=2 |----- --->| Y->8 | 701 | | : +------+ \ +-------+ 702 | CPU 1 | : | A=1 | \ --->| C->&Y | 703 | | +------+ | +-------+ 704 | | wwwwwwwwwwwwwwww | : : 705 | | +------+ | : : 706 | | : | C=&B |--- | : : +-------+ 707 | | : +------+ \ | +-------+ | | 708 | |------>| D=4 | ----------->| C->&B |------>| | 709 | | +------+ | +-------+ | | 710 +-------+ : : | : : | | 711 | : : | | 712 | : : | CPU 2 | 713 | +-------+ | | 714 | | X->9 |------>| | 715 | +-------+ | | 716 Makes sure all effects ---> \ ddddddddddddddddd | | 717 prior to the store of C \ +-------+ | | 718 are perceptible to ----->| B->2 |------>| | 719 subsequent loads +-------+ | | 720 : : +-------+ 721 722 723And thirdly, a read barrier acts as a partial order on loads. Consider the 724following sequence of events: 725 726 CPU 1 CPU 2 727 ======================= ======================= 728 { A = 0, B = 9 } 729 STORE A=1 730 <write barrier> 731 STORE B=2 732 LOAD B 733 LOAD A 734 735Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in 736some effectively random order, despite the write barrier issued by CPU 1: 737 738 +-------+ : : : : 739 | | +------+ +-------+ 740 | |------>| A=1 |------ --->| A->0 | 741 | | +------+ \ +-------+ 742 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | 743 | | +------+ | +-------+ 744 | |------>| B=2 |--- | : : 745 | | +------+ \ | : : +-------+ 746 +-------+ : : \ | +-------+ | | 747 ---------->| B->2 |------>| | 748 | +-------+ | CPU 2 | 749 | | A->0 |------>| | 750 | +-------+ | | 751 | : : +-------+ 752 \ : : 753 \ +-------+ 754 ---->| A->1 | 755 +-------+ 756 : : 757 758 759If, however, a read barrier were to be placed between the load of B and the 760load of A on CPU 2: 761 762 CPU 1 CPU 2 763 ======================= ======================= 764 { A = 0, B = 9 } 765 STORE A=1 766 <write barrier> 767 STORE B=2 768 LOAD B 769 <read barrier> 770 LOAD A 771 772then the partial ordering imposed by CPU 1 will be perceived correctly by CPU 7732: 774 775 +-------+ : : : : 776 | | +------+ +-------+ 777 | |------>| A=1 |------ --->| A->0 | 778 | | +------+ \ +-------+ 779 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | 780 | | +------+ | +-------+ 781 | |------>| B=2 |--- | : : 782 | | +------+ \ | : : +-------+ 783 +-------+ : : \ | +-------+ | | 784 ---------->| B->2 |------>| | 785 | +-------+ | CPU 2 | 786 | : : | | 787 | : : | | 788 At this point the read ----> \ rrrrrrrrrrrrrrrrr | | 789 barrier causes all effects \ +-------+ | | 790 prior to the storage of B ---->| A->1 |------>| | 791 to be perceptible to CPU 2 +-------+ | | 792 : : +-------+ 793 794 795To illustrate this more completely, consider what could happen if the code 796contained a load of A either side of the read barrier: 797 798 CPU 1 CPU 2 799 ======================= ======================= 800 { A = 0, B = 9 } 801 STORE A=1 802 <write barrier> 803 STORE B=2 804 LOAD B 805 LOAD A [first load of A] 806 <read barrier> 807 LOAD A [second load of A] 808 809Even though the two loads of A both occur after the load of B, they may both 810come up with different values: 811 812 +-------+ : : : : 813 | | +------+ +-------+ 814 | |------>| A=1 |------ --->| A->0 | 815 | | +------+ \ +-------+ 816 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | 817 | | +------+ | +-------+ 818 | |------>| B=2 |--- | : : 819 | | +------+ \ | : : +-------+ 820 +-------+ : : \ | +-------+ | | 821 ---------->| B->2 |------>| | 822 | +-------+ | CPU 2 | 823 | : : | | 824 | : : | | 825 | +-------+ | | 826 | | A->0 |------>| 1st | 827 | +-------+ | | 828 At this point the read ----> \ rrrrrrrrrrrrrrrrr | | 829 barrier causes all effects \ +-------+ | | 830 prior to the storage of B ---->| A->1 |------>| 2nd | 831 to be perceptible to CPU 2 +-------+ | | 832 : : +-------+ 833 834 835But it may be that the update to A from CPU 1 becomes perceptible to CPU 2 836before the read barrier completes anyway: 837 838 +-------+ : : : : 839 | | +------+ +-------+ 840 | |------>| A=1 |------ --->| A->0 | 841 | | +------+ \ +-------+ 842 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 | 843 | | +------+ | +-------+ 844 | |------>| B=2 |--- | : : 845 | | +------+ \ | : : +-------+ 846 +-------+ : : \ | +-------+ | | 847 ---------->| B->2 |------>| | 848 | +-------+ | CPU 2 | 849 | : : | | 850 \ : : | | 851 \ +-------+ | | 852 ---->| A->1 |------>| 1st | 853 +-------+ | | 854 rrrrrrrrrrrrrrrrr | | 855 +-------+ | | 856 | A->1 |------>| 2nd | 857 +-------+ | | 858 : : +-------+ 859 860 861The guarantee is that the second load will always come up with A == 1 if the 862load of B came up with B == 2. No such guarantee exists for the first load of 863A; that may come up with either A == 0 or A == 1. 864 865 866READ MEMORY BARRIERS VS LOAD SPECULATION 867---------------------------------------- 868 869Many CPUs speculate with loads: that is they see that they will need to load an 870item from memory, and they find a time where they're not using the bus for any 871other loads, and so do the load in advance - even though they haven't actually 872got to that point in the instruction execution flow yet. This permits the 873actual load instruction to potentially complete immediately because the CPU 874already has the value to hand. 875 876It may turn out that the CPU didn't actually need the value - perhaps because a 877branch circumvented the load - in which case it can discard the value or just 878cache it for later use. 879 880Consider: 881 882 CPU 1 CPU 2 883 ======================= ======================= 884 LOAD B 885 DIVIDE } Divide instructions generally 886 DIVIDE } take a long time to perform 887 LOAD A 888 889Which might appear as this: 890 891 : : +-------+ 892 +-------+ | | 893 --->| B->2 |------>| | 894 +-------+ | CPU 2 | 895 : :DIVIDE | | 896 +-------+ | | 897 The CPU being busy doing a ---> --->| A->0 |~~~~ | | 898 division speculates on the +-------+ ~ | | 899 LOAD of A : : ~ | | 900 : :DIVIDE | | 901 : : ~ | | 902 Once the divisions are complete --> : : ~-->| | 903 the CPU can then perform the : : | | 904 LOAD with immediate effect : : +-------+ 905 906 907Placing a read barrier or a data dependency barrier just before the second 908load: 909 910 CPU 1 CPU 2 911 ======================= ======================= 912 LOAD B 913 DIVIDE 914 DIVIDE 915 <read barrier> 916 LOAD A 917 918will force any value speculatively obtained to be reconsidered to an extent 919dependent on the type of barrier used. If there was no change made to the 920speculated memory location, then the speculated value will just be used: 921 922 : : +-------+ 923 +-------+ | | 924 --->| B->2 |------>| | 925 +-------+ | CPU 2 | 926 : :DIVIDE | | 927 +-------+ | | 928 The CPU being busy doing a ---> --->| A->0 |~~~~ | | 929 division speculates on the +-------+ ~ | | 930 LOAD of A : : ~ | | 931 : :DIVIDE | | 932 : : ~ | | 933 : : ~ | | 934 rrrrrrrrrrrrrrrr~ | | 935 : : ~ | | 936 : : ~-->| | 937 : : | | 938 : : +-------+ 939 940 941but if there was an update or an invalidation from another CPU pending, then 942the speculation will be cancelled and the value reloaded: 943 944 : : +-------+ 945 +-------+ | | 946 --->| B->2 |------>| | 947 +-------+ | CPU 2 | 948 : :DIVIDE | | 949 +-------+ | | 950 The CPU being busy doing a ---> --->| A->0 |~~~~ | | 951 division speculates on the +-------+ ~ | | 952 LOAD of A : : ~ | | 953 : :DIVIDE | | 954 : : ~ | | 955 : : ~ | | 956 rrrrrrrrrrrrrrrrr | | 957 +-------+ | | 958 The speculation is discarded ---> --->| A->1 |------>| | 959 and an updated value is +-------+ | | 960 retrieved : : +-------+ 961 962 963TRANSITIVITY 964------------ 965 966Transitivity is a deeply intuitive notion about ordering that is not 967always provided by real computer systems. The following example 968demonstrates transitivity (also called "cumulativity"): 969 970 CPU 1 CPU 2 CPU 3 971 ======================= ======================= ======================= 972 { X = 0, Y = 0 } 973 STORE X=1 LOAD X STORE Y=1 974 <general barrier> <general barrier> 975 LOAD Y LOAD X 976 977Suppose that CPU 2's load from X returns 1 and its load from Y returns 0. 978This indicates that CPU 2's load from X in some sense follows CPU 1's 979store to X and that CPU 2's load from Y in some sense preceded CPU 3's 980store to Y. The question is then "Can CPU 3's load from X return 0?" 981 982Because CPU 2's load from X in some sense came after CPU 1's store, it 983is natural to expect that CPU 3's load from X must therefore return 1. 984This expectation is an example of transitivity: if a load executing on 985CPU A follows a load from the same variable executing on CPU B, then 986CPU A's load must either return the same value that CPU B's load did, 987or must return some later value. 988 989In the Linux kernel, use of general memory barriers guarantees 990transitivity. Therefore, in the above example, if CPU 2's load from X 991returns 1 and its load from Y returns 0, then CPU 3's load from X must 992also return 1. 993 994However, transitivity is -not- guaranteed for read or write barriers. 995For example, suppose that CPU 2's general barrier in the above example 996is changed to a read barrier as shown below: 997 998 CPU 1 CPU 2 CPU 3 999 ======================= ======================= ======================= 1000 { X = 0, Y = 0 } 1001 STORE X=1 LOAD X STORE Y=1 1002 <read barrier> <general barrier> 1003 LOAD Y LOAD X 1004 1005This substitution destroys transitivity: in this example, it is perfectly 1006legal for CPU 2's load from X to return 1, its load from Y to return 0, 1007and CPU 3's load from X to return 0. 1008 1009The key point is that although CPU 2's read barrier orders its pair 1010of loads, it does not guarantee to order CPU 1's store. Therefore, if 1011this example runs on a system where CPUs 1 and 2 share a store buffer 1012or a level of cache, CPU 2 might have early access to CPU 1's writes. 1013General barriers are therefore required to ensure that all CPUs agree 1014on the combined order of CPU 1's and CPU 2's accesses. 1015 1016To reiterate, if your code requires transitivity, use general barriers 1017throughout. 1018 1019 1020======================== 1021EXPLICIT KERNEL BARRIERS 1022======================== 1023 1024The Linux kernel has a variety of different barriers that act at different 1025levels: 1026 1027 (*) Compiler barrier. 1028 1029 (*) CPU memory barriers. 1030 1031 (*) MMIO write barrier. 1032 1033 1034COMPILER BARRIER 1035---------------- 1036 1037The Linux kernel has an explicit compiler barrier function that prevents the 1038compiler from moving the memory accesses either side of it to the other side: 1039 1040 barrier(); 1041 1042This is a general barrier - lesser varieties of compiler barrier do not exist. 1043 1044The compiler barrier has no direct effect on the CPU, which may then reorder 1045things however it wishes. 1046 1047 1048CPU MEMORY BARRIERS 1049------------------- 1050 1051The Linux kernel has eight basic CPU memory barriers: 1052 1053 TYPE MANDATORY SMP CONDITIONAL 1054 =============== ======================= =========================== 1055 GENERAL mb() smp_mb() 1056 WRITE wmb() smp_wmb() 1057 READ rmb() smp_rmb() 1058 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends() 1059 1060 1061All memory barriers except the data dependency barriers imply a compiler 1062barrier. Data dependencies do not impose any additional compiler ordering. 1063 1064Aside: In the case of data dependencies, the compiler would be expected to 1065issue the loads in the correct order (eg. `a[b]` would have to load the value 1066of b before loading a[b]), however there is no guarantee in the C specification 1067that the compiler may not speculate the value of b (eg. is equal to 1) and load 1068a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the 1069problem of a compiler reloading b after having loaded a[b], thus having a newer 1070copy of b than a[b]. A consensus has not yet been reached about these problems, 1071however the ACCESS_ONCE macro is a good place to start looking. 1072 1073SMP memory barriers are reduced to compiler barriers on uniprocessor compiled 1074systems because it is assumed that a CPU will appear to be self-consistent, 1075and will order overlapping accesses correctly with respect to itself. 1076 1077[!] Note that SMP memory barriers _must_ be used to control the ordering of 1078references to shared memory on SMP systems, though the use of locking instead 1079is sufficient. 1080 1081Mandatory barriers should not be used to control SMP effects, since mandatory 1082barriers unnecessarily impose overhead on UP systems. They may, however, be 1083used to control MMIO effects on accesses through relaxed memory I/O windows. 1084These are required even on non-SMP systems as they affect the order in which 1085memory operations appear to a device by prohibiting both the compiler and the 1086CPU from reordering them. 1087 1088 1089There are some more advanced barrier functions: 1090 1091 (*) set_mb(var, value) 1092 1093 This assigns the value to the variable and then inserts a full memory 1094 barrier after it, depending on the function. It isn't guaranteed to 1095 insert anything more than a compiler barrier in a UP compilation. 1096 1097 1098 (*) smp_mb__before_atomic_dec(); 1099 (*) smp_mb__after_atomic_dec(); 1100 (*) smp_mb__before_atomic_inc(); 1101 (*) smp_mb__after_atomic_inc(); 1102 1103 These are for use with atomic add, subtract, increment and decrement 1104 functions that don't return a value, especially when used for reference 1105 counting. These functions do not imply memory barriers. 1106 1107 As an example, consider a piece of code that marks an object as being dead 1108 and then decrements the object's reference count: 1109 1110 obj->dead = 1; 1111 smp_mb__before_atomic_dec(); 1112 atomic_dec(&obj->ref_count); 1113 1114 This makes sure that the death mark on the object is perceived to be set 1115 *before* the reference counter is decremented. 1116 1117 See Documentation/atomic_ops.txt for more information. See the "Atomic 1118 operations" subsection for information on where to use these. 1119 1120 1121 (*) smp_mb__before_clear_bit(void); 1122 (*) smp_mb__after_clear_bit(void); 1123 1124 These are for use similar to the atomic inc/dec barriers. These are 1125 typically used for bitwise unlocking operations, so care must be taken as 1126 there are no implicit memory barriers here either. 1127 1128 Consider implementing an unlock operation of some nature by clearing a 1129 locking bit. The clear_bit() would then need to be barriered like this: 1130 1131 smp_mb__before_clear_bit(); 1132 clear_bit( ... ); 1133 1134 This prevents memory operations before the clear leaking to after it. See 1135 the subsection on "Locking Functions" with reference to UNLOCK operation 1136 implications. 1137 1138 See Documentation/atomic_ops.txt for more information. See the "Atomic 1139 operations" subsection for information on where to use these. 1140 1141 1142MMIO WRITE BARRIER 1143------------------ 1144 1145The Linux kernel also has a special barrier for use with memory-mapped I/O 1146writes: 1147 1148 mmiowb(); 1149 1150This is a variation on the mandatory write barrier that causes writes to weakly 1151ordered I/O regions to be partially ordered. Its effects may go beyond the 1152CPU->Hardware interface and actually affect the hardware at some level. 1153 1154See the subsection "Locks vs I/O accesses" for more information. 1155 1156 1157=============================== 1158IMPLICIT KERNEL MEMORY BARRIERS 1159=============================== 1160 1161Some of the other functions in the linux kernel imply memory barriers, amongst 1162which are locking and scheduling functions. 1163 1164This specification is a _minimum_ guarantee; any particular architecture may 1165provide more substantial guarantees, but these may not be relied upon outside 1166of arch specific code. 1167 1168 1169LOCKING FUNCTIONS 1170----------------- 1171 1172The Linux kernel has a number of locking constructs: 1173 1174 (*) spin locks 1175 (*) R/W spin locks 1176 (*) mutexes 1177 (*) semaphores 1178 (*) R/W semaphores 1179 (*) RCU 1180 1181In all cases there are variants on "LOCK" operations and "UNLOCK" operations 1182for each construct. These operations all imply certain barriers: 1183 1184 (1) LOCK operation implication: 1185 1186 Memory operations issued after the LOCK will be completed after the LOCK 1187 operation has completed. 1188 1189 Memory operations issued before the LOCK may be completed after the LOCK 1190 operation has completed. 1191 1192 (2) UNLOCK operation implication: 1193 1194 Memory operations issued before the UNLOCK will be completed before the 1195 UNLOCK operation has completed. 1196 1197 Memory operations issued after the UNLOCK may be completed before the 1198 UNLOCK operation has completed. 1199 1200 (3) LOCK vs LOCK implication: 1201 1202 All LOCK operations issued before another LOCK operation will be completed 1203 before that LOCK operation. 1204 1205 (4) LOCK vs UNLOCK implication: 1206 1207 All LOCK operations issued before an UNLOCK operation will be completed 1208 before the UNLOCK operation. 1209 1210 All UNLOCK operations issued before a LOCK operation will be completed 1211 before the LOCK operation. 1212 1213 (5) Failed conditional LOCK implication: 1214 1215 Certain variants of the LOCK operation may fail, either due to being 1216 unable to get the lock immediately, or due to receiving an unblocked 1217 signal whilst asleep waiting for the lock to become available. Failed 1218 locks do not imply any sort of barrier. 1219 1220Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is 1221equivalent to a full barrier, but a LOCK followed by an UNLOCK is not. 1222 1223[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way 1224 barriers is that the effects of instructions outside of a critical section 1225 may seep into the inside of the critical section. 1226 1227A LOCK followed by an UNLOCK may not be assumed to be full memory barrier 1228because it is possible for an access preceding the LOCK to happen after the 1229LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the 1230two accesses can themselves then cross: 1231 1232 *A = a; 1233 LOCK 1234 UNLOCK 1235 *B = b; 1236 1237may occur as: 1238 1239 LOCK, STORE *B, STORE *A, UNLOCK 1240 1241Locks and semaphores may not provide any guarantee of ordering on UP compiled 1242systems, and so cannot be counted on in such a situation to actually achieve 1243anything at all - especially with respect to I/O accesses - unless combined 1244with interrupt disabling operations. 1245 1246See also the section on "Inter-CPU locking barrier effects". 1247 1248 1249As an example, consider the following: 1250 1251 *A = a; 1252 *B = b; 1253 LOCK 1254 *C = c; 1255 *D = d; 1256 UNLOCK 1257 *E = e; 1258 *F = f; 1259 1260The following sequence of events is acceptable: 1261 1262 LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK 1263 1264 [+] Note that {*F,*A} indicates a combined access. 1265 1266But none of the following are: 1267 1268 {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E 1269 *A, *B, *C, LOCK, *D, UNLOCK, *E, *F 1270 *A, *B, LOCK, *C, UNLOCK, *D, *E, *F 1271 *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E 1272 1273 1274 1275INTERRUPT DISABLING FUNCTIONS 1276----------------------------- 1277 1278Functions that disable interrupts (LOCK equivalent) and enable interrupts 1279(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O 1280barriers are required in such a situation, they must be provided from some 1281other means. 1282 1283 1284SLEEP AND WAKE-UP FUNCTIONS 1285--------------------------- 1286 1287Sleeping and waking on an event flagged in global data can be viewed as an 1288interaction between two pieces of data: the task state of the task waiting for 1289the event and the global data used to indicate the event. To make sure that 1290these appear to happen in the right order, the primitives to begin the process 1291of going to sleep, and the primitives to initiate a wake up imply certain 1292barriers. 1293 1294Firstly, the sleeper normally follows something like this sequence of events: 1295 1296 for (;;) { 1297 set_current_state(TASK_UNINTERRUPTIBLE); 1298 if (event_indicated) 1299 break; 1300 schedule(); 1301 } 1302 1303A general memory barrier is interpolated automatically by set_current_state() 1304after it has altered the task state: 1305 1306 CPU 1 1307 =============================== 1308 set_current_state(); 1309 set_mb(); 1310 STORE current->state 1311 <general barrier> 1312 LOAD event_indicated 1313 1314set_current_state() may be wrapped by: 1315 1316 prepare_to_wait(); 1317 prepare_to_wait_exclusive(); 1318 1319which therefore also imply a general memory barrier after setting the state. 1320The whole sequence above is available in various canned forms, all of which 1321interpolate the memory barrier in the right place: 1322 1323 wait_event(); 1324 wait_event_interruptible(); 1325 wait_event_interruptible_exclusive(); 1326 wait_event_interruptible_timeout(); 1327 wait_event_killable(); 1328 wait_event_timeout(); 1329 wait_on_bit(); 1330 wait_on_bit_lock(); 1331 1332 1333Secondly, code that performs a wake up normally follows something like this: 1334 1335 event_indicated = 1; 1336 wake_up(&event_wait_queue); 1337 1338or: 1339 1340 event_indicated = 1; 1341 wake_up_process(event_daemon); 1342 1343A write memory barrier is implied by wake_up() and co. if and only if they wake 1344something up. The barrier occurs before the task state is cleared, and so sits 1345between the STORE to indicate the event and the STORE to set TASK_RUNNING: 1346 1347 CPU 1 CPU 2 1348 =============================== =============================== 1349 set_current_state(); STORE event_indicated 1350 set_mb(); wake_up(); 1351 STORE current->state <write barrier> 1352 <general barrier> STORE current->state 1353 LOAD event_indicated 1354 1355The available waker functions include: 1356 1357 complete(); 1358 wake_up(); 1359 wake_up_all(); 1360 wake_up_bit(); 1361 wake_up_interruptible(); 1362 wake_up_interruptible_all(); 1363 wake_up_interruptible_nr(); 1364 wake_up_interruptible_poll(); 1365 wake_up_interruptible_sync(); 1366 wake_up_interruptible_sync_poll(); 1367 wake_up_locked(); 1368 wake_up_locked_poll(); 1369 wake_up_nr(); 1370 wake_up_poll(); 1371 wake_up_process(); 1372 1373 1374[!] Note that the memory barriers implied by the sleeper and the waker do _not_ 1375order multiple stores before the wake-up with respect to loads of those stored 1376values after the sleeper has called set_current_state(). For instance, if the 1377sleeper does: 1378 1379 set_current_state(TASK_INTERRUPTIBLE); 1380 if (event_indicated) 1381 break; 1382 __set_current_state(TASK_RUNNING); 1383 do_something(my_data); 1384 1385and the waker does: 1386 1387 my_data = value; 1388 event_indicated = 1; 1389 wake_up(&event_wait_queue); 1390 1391there's no guarantee that the change to event_indicated will be perceived by 1392the sleeper as coming after the change to my_data. In such a circumstance, the 1393code on both sides must interpolate its own memory barriers between the 1394separate data accesses. Thus the above sleeper ought to do: 1395 1396 set_current_state(TASK_INTERRUPTIBLE); 1397 if (event_indicated) { 1398 smp_rmb(); 1399 do_something(my_data); 1400 } 1401 1402and the waker should do: 1403 1404 my_data = value; 1405 smp_wmb(); 1406 event_indicated = 1; 1407 wake_up(&event_wait_queue); 1408 1409 1410MISCELLANEOUS FUNCTIONS 1411----------------------- 1412 1413Other functions that imply barriers: 1414 1415 (*) schedule() and similar imply full memory barriers. 1416 1417 1418================================= 1419INTER-CPU LOCKING BARRIER EFFECTS 1420================================= 1421 1422On SMP systems locking primitives give a more substantial form of barrier: one 1423that does affect memory access ordering on other CPUs, within the context of 1424conflict on any particular lock. 1425 1426 1427LOCKS VS MEMORY ACCESSES 1428------------------------ 1429 1430Consider the following: the system has a pair of spinlocks (M) and (Q), and 1431three CPUs; then should the following sequence of events occur: 1432 1433 CPU 1 CPU 2 1434 =============================== =============================== 1435 *A = a; *E = e; 1436 LOCK M LOCK Q 1437 *B = b; *F = f; 1438 *C = c; *G = g; 1439 UNLOCK M UNLOCK Q 1440 *D = d; *H = h; 1441 1442Then there is no guarantee as to what order CPU 3 will see the accesses to *A 1443through *H occur in, other than the constraints imposed by the separate locks 1444on the separate CPUs. It might, for example, see: 1445 1446 *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M 1447 1448But it won't see any of: 1449 1450 *B, *C or *D preceding LOCK M 1451 *A, *B or *C following UNLOCK M 1452 *F, *G or *H preceding LOCK Q 1453 *E, *F or *G following UNLOCK Q 1454 1455 1456However, if the following occurs: 1457 1458 CPU 1 CPU 2 1459 =============================== =============================== 1460 *A = a; 1461 LOCK M [1] 1462 *B = b; 1463 *C = c; 1464 UNLOCK M [1] 1465 *D = d; *E = e; 1466 LOCK M [2] 1467 *F = f; 1468 *G = g; 1469 UNLOCK M [2] 1470 *H = h; 1471 1472CPU 3 might see: 1473 1474 *E, LOCK M [1], *C, *B, *A, UNLOCK M [1], 1475 LOCK M [2], *H, *F, *G, UNLOCK M [2], *D 1476 1477But assuming CPU 1 gets the lock first, CPU 3 won't see any of: 1478 1479 *B, *C, *D, *F, *G or *H preceding LOCK M [1] 1480 *A, *B or *C following UNLOCK M [1] 1481 *F, *G or *H preceding LOCK M [2] 1482 *A, *B, *C, *E, *F or *G following UNLOCK M [2] 1483 1484 1485LOCKS VS I/O ACCESSES 1486--------------------- 1487 1488Under certain circumstances (especially involving NUMA), I/O accesses within 1489two spinlocked sections on two different CPUs may be seen as interleaved by the 1490PCI bridge, because the PCI bridge does not necessarily participate in the 1491cache-coherence protocol, and is therefore incapable of issuing the required 1492read memory barriers. 1493 1494For example: 1495 1496 CPU 1 CPU 2 1497 =============================== =============================== 1498 spin_lock(Q) 1499 writel(0, ADDR) 1500 writel(1, DATA); 1501 spin_unlock(Q); 1502 spin_lock(Q); 1503 writel(4, ADDR); 1504 writel(5, DATA); 1505 spin_unlock(Q); 1506 1507may be seen by the PCI bridge as follows: 1508 1509 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5 1510 1511which would probably cause the hardware to malfunction. 1512 1513 1514What is necessary here is to intervene with an mmiowb() before dropping the 1515spinlock, for example: 1516 1517 CPU 1 CPU 2 1518 =============================== =============================== 1519 spin_lock(Q) 1520 writel(0, ADDR) 1521 writel(1, DATA); 1522 mmiowb(); 1523 spin_unlock(Q); 1524 spin_lock(Q); 1525 writel(4, ADDR); 1526 writel(5, DATA); 1527 mmiowb(); 1528 spin_unlock(Q); 1529 1530this will ensure that the two stores issued on CPU 1 appear at the PCI bridge 1531before either of the stores issued on CPU 2. 1532 1533 1534Furthermore, following a store by a load from the same device obviates the need 1535for the mmiowb(), because the load forces the store to complete before the load 1536is performed: 1537 1538 CPU 1 CPU 2 1539 =============================== =============================== 1540 spin_lock(Q) 1541 writel(0, ADDR) 1542 a = readl(DATA); 1543 spin_unlock(Q); 1544 spin_lock(Q); 1545 writel(4, ADDR); 1546 b = readl(DATA); 1547 spin_unlock(Q); 1548 1549 1550See Documentation/DocBook/deviceiobook.tmpl for more information. 1551 1552 1553================================= 1554WHERE ARE MEMORY BARRIERS NEEDED? 1555================================= 1556 1557Under normal operation, memory operation reordering is generally not going to 1558be a problem as a single-threaded linear piece of code will still appear to 1559work correctly, even if it's in an SMP kernel. There are, however, four 1560circumstances in which reordering definitely _could_ be a problem: 1561 1562 (*) Interprocessor interaction. 1563 1564 (*) Atomic operations. 1565 1566 (*) Accessing devices. 1567 1568 (*) Interrupts. 1569 1570 1571INTERPROCESSOR INTERACTION 1572-------------------------- 1573 1574When there's a system with more than one processor, more than one CPU in the 1575system may be working on the same data set at the same time. This can cause 1576synchronisation problems, and the usual way of dealing with them is to use 1577locks. Locks, however, are quite expensive, and so it may be preferable to 1578operate without the use of a lock if at all possible. In such a case 1579operations that affect both CPUs may have to be carefully ordered to prevent 1580a malfunction. 1581 1582Consider, for example, the R/W semaphore slow path. Here a waiting process is 1583queued on the semaphore, by virtue of it having a piece of its stack linked to 1584the semaphore's list of waiting processes: 1585 1586 struct rw_semaphore { 1587 ... 1588 spinlock_t lock; 1589 struct list_head waiters; 1590 }; 1591 1592 struct rwsem_waiter { 1593 struct list_head list; 1594 struct task_struct *task; 1595 }; 1596 1597To wake up a particular waiter, the up_read() or up_write() functions have to: 1598 1599 (1) read the next pointer from this waiter's record to know as to where the 1600 next waiter record is; 1601 1602 (2) read the pointer to the waiter's task structure; 1603 1604 (3) clear the task pointer to tell the waiter it has been given the semaphore; 1605 1606 (4) call wake_up_process() on the task; and 1607 1608 (5) release the reference held on the waiter's task struct. 1609 1610In other words, it has to perform this sequence of events: 1611 1612 LOAD waiter->list.next; 1613 LOAD waiter->task; 1614 STORE waiter->task; 1615 CALL wakeup 1616 RELEASE task 1617 1618and if any of these steps occur out of order, then the whole thing may 1619malfunction. 1620 1621Once it has queued itself and dropped the semaphore lock, the waiter does not 1622get the lock again; it instead just waits for its task pointer to be cleared 1623before proceeding. Since the record is on the waiter's stack, this means that 1624if the task pointer is cleared _before_ the next pointer in the list is read, 1625another CPU might start processing the waiter and might clobber the waiter's 1626stack before the up*() function has a chance to read the next pointer. 1627 1628Consider then what might happen to the above sequence of events: 1629 1630 CPU 1 CPU 2 1631 =============================== =============================== 1632 down_xxx() 1633 Queue waiter 1634 Sleep 1635 up_yyy() 1636 LOAD waiter->task; 1637 STORE waiter->task; 1638 Woken up by other event 1639 <preempt> 1640 Resume processing 1641 down_xxx() returns 1642 call foo() 1643 foo() clobbers *waiter 1644 </preempt> 1645 LOAD waiter->list.next; 1646 --- OOPS --- 1647 1648This could be dealt with using the semaphore lock, but then the down_xxx() 1649function has to needlessly get the spinlock again after being woken up. 1650 1651The way to deal with this is to insert a general SMP memory barrier: 1652 1653 LOAD waiter->list.next; 1654 LOAD waiter->task; 1655 smp_mb(); 1656 STORE waiter->task; 1657 CALL wakeup 1658 RELEASE task 1659 1660In this case, the barrier makes a guarantee that all memory accesses before the 1661barrier will appear to happen before all the memory accesses after the barrier 1662with respect to the other CPUs on the system. It does _not_ guarantee that all 1663the memory accesses before the barrier will be complete by the time the barrier 1664instruction itself is complete. 1665 1666On a UP system - where this wouldn't be a problem - the smp_mb() is just a 1667compiler barrier, thus making sure the compiler emits the instructions in the 1668right order without actually intervening in the CPU. Since there's only one 1669CPU, that CPU's dependency ordering logic will take care of everything else. 1670 1671 1672ATOMIC OPERATIONS 1673----------------- 1674 1675Whilst they are technically interprocessor interaction considerations, atomic 1676operations are noted specially as some of them imply full memory barriers and 1677some don't, but they're very heavily relied on as a group throughout the 1678kernel. 1679 1680Any atomic operation that modifies some state in memory and returns information 1681about the state (old or new) implies an SMP-conditional general memory barrier 1682(smp_mb()) on each side of the actual operation (with the exception of 1683explicit lock operations, described later). These include: 1684 1685 xchg(); 1686 cmpxchg(); 1687 atomic_cmpxchg(); 1688 atomic_inc_return(); 1689 atomic_dec_return(); 1690 atomic_add_return(); 1691 atomic_sub_return(); 1692 atomic_inc_and_test(); 1693 atomic_dec_and_test(); 1694 atomic_sub_and_test(); 1695 atomic_add_negative(); 1696 atomic_add_unless(); /* when succeeds (returns 1) */ 1697 test_and_set_bit(); 1698 test_and_clear_bit(); 1699 test_and_change_bit(); 1700 1701These are used for such things as implementing LOCK-class and UNLOCK-class 1702operations and adjusting reference counters towards object destruction, and as 1703such the implicit memory barrier effects are necessary. 1704 1705 1706The following operations are potential problems as they do _not_ imply memory 1707barriers, but might be used for implementing such things as UNLOCK-class 1708operations: 1709 1710 atomic_set(); 1711 set_bit(); 1712 clear_bit(); 1713 change_bit(); 1714 1715With these the appropriate explicit memory barrier should be used if necessary 1716(smp_mb__before_clear_bit() for instance). 1717 1718 1719The following also do _not_ imply memory barriers, and so may require explicit 1720memory barriers under some circumstances (smp_mb__before_atomic_dec() for 1721instance): 1722 1723 atomic_add(); 1724 atomic_sub(); 1725 atomic_inc(); 1726 atomic_dec(); 1727 1728If they're used for statistics generation, then they probably don't need memory 1729barriers, unless there's a coupling between statistical data. 1730 1731If they're used for reference counting on an object to control its lifetime, 1732they probably don't need memory barriers because either the reference count 1733will be adjusted inside a locked section, or the caller will already hold 1734sufficient references to make the lock, and thus a memory barrier unnecessary. 1735 1736If they're used for constructing a lock of some description, then they probably 1737do need memory barriers as a lock primitive generally has to do things in a 1738specific order. 1739 1740Basically, each usage case has to be carefully considered as to whether memory 1741barriers are needed or not. 1742 1743The following operations are special locking primitives: 1744 1745 test_and_set_bit_lock(); 1746 clear_bit_unlock(); 1747 __clear_bit_unlock(); 1748 1749These implement LOCK-class and UNLOCK-class operations. These should be used in 1750preference to other operations when implementing locking primitives, because 1751their implementations can be optimised on many architectures. 1752 1753[!] Note that special memory barrier primitives are available for these 1754situations because on some CPUs the atomic instructions used imply full memory 1755barriers, and so barrier instructions are superfluous in conjunction with them, 1756and in such cases the special barrier primitives will be no-ops. 1757 1758See Documentation/atomic_ops.txt for more information. 1759 1760 1761ACCESSING DEVICES 1762----------------- 1763 1764Many devices can be memory mapped, and so appear to the CPU as if they're just 1765a set of memory locations. To control such a device, the driver usually has to 1766make the right memory accesses in exactly the right order. 1767 1768However, having a clever CPU or a clever compiler creates a potential problem 1769in that the carefully sequenced accesses in the driver code won't reach the 1770device in the requisite order if the CPU or the compiler thinks it is more 1771efficient to reorder, combine or merge accesses - something that would cause 1772the device to malfunction. 1773 1774Inside of the Linux kernel, I/O should be done through the appropriate accessor 1775routines - such as inb() or writel() - which know how to make such accesses 1776appropriately sequential. Whilst this, for the most part, renders the explicit 1777use of memory barriers unnecessary, there are a couple of situations where they 1778might be needed: 1779 1780 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and 1781 so for _all_ general drivers locks should be used and mmiowb() must be 1782 issued prior to unlocking the critical section. 1783 1784 (2) If the accessor functions are used to refer to an I/O memory window with 1785 relaxed memory access properties, then _mandatory_ memory barriers are 1786 required to enforce ordering. 1787 1788See Documentation/DocBook/deviceiobook.tmpl for more information. 1789 1790 1791INTERRUPTS 1792---------- 1793 1794A driver may be interrupted by its own interrupt service routine, and thus the 1795two parts of the driver may interfere with each other's attempts to control or 1796access the device. 1797 1798This may be alleviated - at least in part - by disabling local interrupts (a 1799form of locking), such that the critical operations are all contained within 1800the interrupt-disabled section in the driver. Whilst the driver's interrupt 1801routine is executing, the driver's core may not run on the same CPU, and its 1802interrupt is not permitted to happen again until the current interrupt has been 1803handled, thus the interrupt handler does not need to lock against that. 1804 1805However, consider a driver that was talking to an ethernet card that sports an 1806address register and a data register. If that driver's core talks to the card 1807under interrupt-disablement and then the driver's interrupt handler is invoked: 1808 1809 LOCAL IRQ DISABLE 1810 writew(ADDR, 3); 1811 writew(DATA, y); 1812 LOCAL IRQ ENABLE 1813 <interrupt> 1814 writew(ADDR, 4); 1815 q = readw(DATA); 1816 </interrupt> 1817 1818The store to the data register might happen after the second store to the 1819address register if ordering rules are sufficiently relaxed: 1820 1821 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA 1822 1823 1824If ordering rules are relaxed, it must be assumed that accesses done inside an 1825interrupt disabled section may leak outside of it and may interleave with 1826accesses performed in an interrupt - and vice versa - unless implicit or 1827explicit barriers are used. 1828 1829Normally this won't be a problem because the I/O accesses done inside such 1830sections will include synchronous load operations on strictly ordered I/O 1831registers that form implicit I/O barriers. If this isn't sufficient then an 1832mmiowb() may need to be used explicitly. 1833 1834 1835A similar situation may occur between an interrupt routine and two routines 1836running on separate CPUs that communicate with each other. If such a case is 1837likely, then interrupt-disabling locks should be used to guarantee ordering. 1838 1839 1840========================== 1841KERNEL I/O BARRIER EFFECTS 1842========================== 1843 1844When accessing I/O memory, drivers should use the appropriate accessor 1845functions: 1846 1847 (*) inX(), outX(): 1848 1849 These are intended to talk to I/O space rather than memory space, but 1850 that's primarily a CPU-specific concept. The i386 and x86_64 processors do 1851 indeed have special I/O space access cycles and instructions, but many 1852 CPUs don't have such a concept. 1853 1854 The PCI bus, amongst others, defines an I/O space concept which - on such 1855 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O 1856 space. However, it may also be mapped as a virtual I/O space in the CPU's 1857 memory map, particularly on those CPUs that don't support alternate I/O 1858 spaces. 1859 1860 Accesses to this space may be fully synchronous (as on i386), but 1861 intermediary bridges (such as the PCI host bridge) may not fully honour 1862 that. 1863 1864 They are guaranteed to be fully ordered with respect to each other. 1865 1866 They are not guaranteed to be fully ordered with respect to other types of 1867 memory and I/O operation. 1868 1869 (*) readX(), writeX(): 1870 1871 Whether these are guaranteed to be fully ordered and uncombined with 1872 respect to each other on the issuing CPU depends on the characteristics 1873 defined for the memory window through which they're accessing. On later 1874 i386 architecture machines, for example, this is controlled by way of the 1875 MTRR registers. 1876 1877 Ordinarily, these will be guaranteed to be fully ordered and uncombined, 1878 provided they're not accessing a prefetchable device. 1879 1880 However, intermediary hardware (such as a PCI bridge) may indulge in 1881 deferral if it so wishes; to flush a store, a load from the same location 1882 is preferred[*], but a load from the same device or from configuration 1883 space should suffice for PCI. 1884 1885 [*] NOTE! attempting to load from the same location as was written to may 1886 cause a malfunction - consider the 16550 Rx/Tx serial registers for 1887 example. 1888 1889 Used with prefetchable I/O memory, an mmiowb() barrier may be required to 1890 force stores to be ordered. 1891 1892 Please refer to the PCI specification for more information on interactions 1893 between PCI transactions. 1894 1895 (*) readX_relaxed() 1896 1897 These are similar to readX(), but are not guaranteed to be ordered in any 1898 way. Be aware that there is no I/O read barrier available. 1899 1900 (*) ioreadX(), iowriteX() 1901 1902 These will perform appropriately for the type of access they're actually 1903 doing, be it inX()/outX() or readX()/writeX(). 1904 1905 1906======================================== 1907ASSUMED MINIMUM EXECUTION ORDERING MODEL 1908======================================== 1909 1910It has to be assumed that the conceptual CPU is weakly-ordered but that it will 1911maintain the appearance of program causality with respect to itself. Some CPUs 1912(such as i386 or x86_64) are more constrained than others (such as powerpc or 1913frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside 1914of arch-specific code. 1915 1916This means that it must be considered that the CPU will execute its instruction 1917stream in any order it feels like - or even in parallel - provided that if an 1918instruction in the stream depends on an earlier instruction, then that 1919earlier instruction must be sufficiently complete[*] before the later 1920instruction may proceed; in other words: provided that the appearance of 1921causality is maintained. 1922 1923 [*] Some instructions have more than one effect - such as changing the 1924 condition codes, changing registers or changing memory - and different 1925 instructions may depend on different effects. 1926 1927A CPU may also discard any instruction sequence that winds up having no 1928ultimate effect. For example, if two adjacent instructions both load an 1929immediate value into the same register, the first may be discarded. 1930 1931 1932Similarly, it has to be assumed that compiler might reorder the instruction 1933stream in any way it sees fit, again provided the appearance of causality is 1934maintained. 1935 1936 1937============================ 1938THE EFFECTS OF THE CPU CACHE 1939============================ 1940 1941The way cached memory operations are perceived across the system is affected to 1942a certain extent by the caches that lie between CPUs and memory, and by the 1943memory coherence system that maintains the consistency of state in the system. 1944 1945As far as the way a CPU interacts with another part of the system through the 1946caches goes, the memory system has to include the CPU's caches, and memory 1947barriers for the most part act at the interface between the CPU and its cache 1948(memory barriers logically act on the dotted line in the following diagram): 1949 1950 <--- CPU ---> : <----------- Memory -----------> 1951 : 1952 +--------+ +--------+ : +--------+ +-----------+ 1953 | | | | : | | | | +--------+ 1954 | CPU | | Memory | : | CPU | | | | | 1955 | Core |--->| Access |----->| Cache |<-->| | | | 1956 | | | Queue | : | | | |--->| Memory | 1957 | | | | : | | | | | | 1958 +--------+ +--------+ : +--------+ | | | | 1959 : | Cache | +--------+ 1960 : | Coherency | 1961 : | Mechanism | +--------+ 1962 +--------+ +--------+ : +--------+ | | | | 1963 | | | | : | | | | | | 1964 | CPU | | Memory | : | CPU | | |--->| Device | 1965 | Core |--->| Access |----->| Cache |<-->| | | | 1966 | | | Queue | : | | | | | | 1967 | | | | : | | | | +--------+ 1968 +--------+ +--------+ : +--------+ +-----------+ 1969 : 1970 : 1971 1972Although any particular load or store may not actually appear outside of the 1973CPU that issued it since it may have been satisfied within the CPU's own cache, 1974it will still appear as if the full memory access had taken place as far as the 1975other CPUs are concerned since the cache coherency mechanisms will migrate the 1976cacheline over to the accessing CPU and propagate the effects upon conflict. 1977 1978The CPU core may execute instructions in any order it deems fit, provided the 1979expected program causality appears to be maintained. Some of the instructions 1980generate load and store operations which then go into the queue of memory 1981accesses to be performed. The core may place these in the queue in any order 1982it wishes, and continue execution until it is forced to wait for an instruction 1983to complete. 1984 1985What memory barriers are concerned with is controlling the order in which 1986accesses cross from the CPU side of things to the memory side of things, and 1987the order in which the effects are perceived to happen by the other observers 1988in the system. 1989 1990[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see 1991their own loads and stores as if they had happened in program order. 1992 1993[!] MMIO or other device accesses may bypass the cache system. This depends on 1994the properties of the memory window through which devices are accessed and/or 1995the use of any special device communication instructions the CPU may have. 1996 1997 1998CACHE COHERENCY 1999--------------- 2000 2001Life isn't quite as simple as it may appear above, however: for while the 2002caches are expected to be coherent, there's no guarantee that that coherency 2003will be ordered. This means that whilst changes made on one CPU will 2004eventually become visible on all CPUs, there's no guarantee that they will 2005become apparent in the same order on those other CPUs. 2006 2007 2008Consider dealing with a system that has a pair of CPUs (1 & 2), each of which 2009has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D): 2010 2011 : 2012 : +--------+ 2013 : +---------+ | | 2014 +--------+ : +--->| Cache A |<------->| | 2015 | | : | +---------+ | | 2016 | CPU 1 |<---+ | | 2017 | | : | +---------+ | | 2018 +--------+ : +--->| Cache B |<------->| | 2019 : +---------+ | | 2020 : | Memory | 2021 : +---------+ | System | 2022 +--------+ : +--->| Cache C |<------->| | 2023 | | : | +---------+ | | 2024 | CPU 2 |<---+ | | 2025 | | : | +---------+ | | 2026 +--------+ : +--->| Cache D |<------->| | 2027 : +---------+ | | 2028 : +--------+ 2029 : 2030 2031Imagine the system has the following properties: 2032 2033 (*) an odd-numbered cache line may be in cache A, cache C or it may still be 2034 resident in memory; 2035 2036 (*) an even-numbered cache line may be in cache B, cache D or it may still be 2037 resident in memory; 2038 2039 (*) whilst the CPU core is interrogating one cache, the other cache may be 2040 making use of the bus to access the rest of the system - perhaps to 2041 displace a dirty cacheline or to do a speculative load; 2042 2043 (*) each cache has a queue of operations that need to be applied to that cache 2044 to maintain coherency with the rest of the system; 2045 2046 (*) the coherency queue is not flushed by normal loads to lines already 2047 present in the cache, even though the contents of the queue may 2048 potentially affect those loads. 2049 2050Imagine, then, that two writes are made on the first CPU, with a write barrier 2051between them to guarantee that they will appear to reach that CPU's caches in 2052the requisite order: 2053 2054 CPU 1 CPU 2 COMMENT 2055 =============== =============== ======================================= 2056 u == 0, v == 1 and p == &u, q == &u 2057 v = 2; 2058 smp_wmb(); Make sure change to v is visible before 2059 change to p 2060 <A:modify v=2> v is now in cache A exclusively 2061 p = &v; 2062 <B:modify p=&v> p is now in cache B exclusively 2063 2064The write memory barrier forces the other CPUs in the system to perceive that 2065the local CPU's caches have apparently been updated in the correct order. But 2066now imagine that the second CPU wants to read those values: 2067 2068 CPU 1 CPU 2 COMMENT 2069 =============== =============== ======================================= 2070 ... 2071 q = p; 2072 x = *q; 2073 2074The above pair of reads may then fail to happen in the expected order, as the 2075cacheline holding p may get updated in one of the second CPU's caches whilst 2076the update to the cacheline holding v is delayed in the other of the second 2077CPU's caches by some other cache event: 2078 2079 CPU 1 CPU 2 COMMENT 2080 =============== =============== ======================================= 2081 u == 0, v == 1 and p == &u, q == &u 2082 v = 2; 2083 smp_wmb(); 2084 <A:modify v=2> <C:busy> 2085 <C:queue v=2> 2086 p = &v; q = p; 2087 <D:request p> 2088 <B:modify p=&v> <D:commit p=&v> 2089 <D:read p> 2090 x = *q; 2091 <C:read *q> Reads from v before v updated in cache 2092 <C:unbusy> 2093 <C:commit v=2> 2094 2095Basically, whilst both cachelines will be updated on CPU 2 eventually, there's 2096no guarantee that, without intervention, the order of update will be the same 2097as that committed on CPU 1. 2098 2099 2100To intervene, we need to interpolate a data dependency barrier or a read 2101barrier between the loads. This will force the cache to commit its coherency 2102queue before processing any further requests: 2103 2104 CPU 1 CPU 2 COMMENT 2105 =============== =============== ======================================= 2106 u == 0, v == 1 and p == &u, q == &u 2107 v = 2; 2108 smp_wmb(); 2109 <A:modify v=2> <C:busy> 2110 <C:queue v=2> 2111 p = &v; q = p; 2112 <D:request p> 2113 <B:modify p=&v> <D:commit p=&v> 2114 <D:read p> 2115 smp_read_barrier_depends() 2116 <C:unbusy> 2117 <C:commit v=2> 2118 x = *q; 2119 <C:read *q> Reads from v after v updated in cache 2120 2121 2122This sort of problem can be encountered on DEC Alpha processors as they have a 2123split cache that improves performance by making better use of the data bus. 2124Whilst most CPUs do imply a data dependency barrier on the read when a memory 2125access depends on a read, not all do, so it may not be relied on. 2126 2127Other CPUs may also have split caches, but must coordinate between the various 2128cachelets for normal memory accesses. The semantics of the Alpha removes the 2129need for coordination in the absence of memory barriers. 2130 2131 2132CACHE COHERENCY VS DMA 2133---------------------- 2134 2135Not all systems maintain cache coherency with respect to devices doing DMA. In 2136such cases, a device attempting DMA may obtain stale data from RAM because 2137dirty cache lines may be resident in the caches of various CPUs, and may not 2138have been written back to RAM yet. To deal with this, the appropriate part of 2139the kernel must flush the overlapping bits of cache on each CPU (and maybe 2140invalidate them as well). 2141 2142In addition, the data DMA'd to RAM by a device may be overwritten by dirty 2143cache lines being written back to RAM from a CPU's cache after the device has 2144installed its own data, or cache lines present in the CPU's cache may simply 2145obscure the fact that RAM has been updated, until at such time as the cacheline 2146is discarded from the CPU's cache and reloaded. To deal with this, the 2147appropriate part of the kernel must invalidate the overlapping bits of the 2148cache on each CPU. 2149 2150See Documentation/cachetlb.txt for more information on cache management. 2151 2152 2153CACHE COHERENCY VS MMIO 2154----------------------- 2155 2156Memory mapped I/O usually takes place through memory locations that are part of 2157a window in the CPU's memory space that has different properties assigned than 2158the usual RAM directed window. 2159 2160Amongst these properties is usually the fact that such accesses bypass the 2161caching entirely and go directly to the device buses. This means MMIO accesses 2162may, in effect, overtake accesses to cached memory that were emitted earlier. 2163A memory barrier isn't sufficient in such a case, but rather the cache must be 2164flushed between the cached memory write and the MMIO access if the two are in 2165any way dependent. 2166 2167 2168========================= 2169THE THINGS CPUS GET UP TO 2170========================= 2171 2172A programmer might take it for granted that the CPU will perform memory 2173operations in exactly the order specified, so that if the CPU is, for example, 2174given the following piece of code to execute: 2175 2176 a = *A; 2177 *B = b; 2178 c = *C; 2179 d = *D; 2180 *E = e; 2181 2182they would then expect that the CPU will complete the memory operation for each 2183instruction before moving on to the next one, leading to a definite sequence of 2184operations as seen by external observers in the system: 2185 2186 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E. 2187 2188 2189Reality is, of course, much messier. With many CPUs and compilers, the above 2190assumption doesn't hold because: 2191 2192 (*) loads are more likely to need to be completed immediately to permit 2193 execution progress, whereas stores can often be deferred without a 2194 problem; 2195 2196 (*) loads may be done speculatively, and the result discarded should it prove 2197 to have been unnecessary; 2198 2199 (*) loads may be done speculatively, leading to the result having been fetched 2200 at the wrong time in the expected sequence of events; 2201 2202 (*) the order of the memory accesses may be rearranged to promote better use 2203 of the CPU buses and caches; 2204 2205 (*) loads and stores may be combined to improve performance when talking to 2206 memory or I/O hardware that can do batched accesses of adjacent locations, 2207 thus cutting down on transaction setup costs (memory and PCI devices may 2208 both be able to do this); and 2209 2210 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency 2211 mechanisms may alleviate this - once the store has actually hit the cache 2212 - there's no guarantee that the coherency management will be propagated in 2213 order to other CPUs. 2214 2215So what another CPU, say, might actually observe from the above piece of code 2216is: 2217 2218 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B 2219 2220 (Where "LOAD {*C,*D}" is a combined load) 2221 2222 2223However, it is guaranteed that a CPU will be self-consistent: it will see its 2224_own_ accesses appear to be correctly ordered, without the need for a memory 2225barrier. For instance with the following code: 2226 2227 U = *A; 2228 *A = V; 2229 *A = W; 2230 X = *A; 2231 *A = Y; 2232 Z = *A; 2233 2234and assuming no intervention by an external influence, it can be assumed that 2235the final result will appear to be: 2236 2237 U == the original value of *A 2238 X == W 2239 Z == Y 2240 *A == Y 2241 2242The code above may cause the CPU to generate the full sequence of memory 2243accesses: 2244 2245 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A 2246 2247in that order, but, without intervention, the sequence may have almost any 2248combination of elements combined or discarded, provided the program's view of 2249the world remains consistent. 2250 2251The compiler may also combine, discard or defer elements of the sequence before 2252the CPU even sees them. 2253 2254For instance: 2255 2256 *A = V; 2257 *A = W; 2258 2259may be reduced to: 2260 2261 *A = W; 2262 2263since, without a write barrier, it can be assumed that the effect of the 2264storage of V to *A is lost. Similarly: 2265 2266 *A = Y; 2267 Z = *A; 2268 2269may, without a memory barrier, be reduced to: 2270 2271 *A = Y; 2272 Z = Y; 2273 2274and the LOAD operation never appear outside of the CPU. 2275 2276 2277AND THEN THERE'S THE ALPHA 2278-------------------------- 2279 2280The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that, 2281some versions of the Alpha CPU have a split data cache, permitting them to have 2282two semantically-related cache lines updated at separate times. This is where 2283the data dependency barrier really becomes necessary as this synchronises both 2284caches with the memory coherence system, thus making it seem like pointer 2285changes vs new data occur in the right order. 2286 2287The Alpha defines the Linux kernel's memory barrier model. 2288 2289See the subsection on "Cache Coherency" above. 2290 2291 2292============ 2293EXAMPLE USES 2294============ 2295 2296CIRCULAR BUFFERS 2297---------------- 2298 2299Memory barriers can be used to implement circular buffering without the need 2300of a lock to serialise the producer with the consumer. See: 2301 2302 Documentation/circular-buffers.txt 2303 2304for details. 2305 2306 2307========== 2308REFERENCES 2309========== 2310 2311Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek, 2312Digital Press) 2313 Chapter 5.2: Physical Address Space Characteristics 2314 Chapter 5.4: Caches and Write Buffers 2315 Chapter 5.5: Data Sharing 2316 Chapter 5.6: Read/Write Ordering 2317 2318AMD64 Architecture Programmer's Manual Volume 2: System Programming 2319 Chapter 7.1: Memory-Access Ordering 2320 Chapter 7.4: Buffering and Combining Memory Writes 2321 2322IA-32 Intel Architecture Software Developer's Manual, Volume 3: 2323System Programming Guide 2324 Chapter 7.1: Locked Atomic Operations 2325 Chapter 7.2: Memory Ordering 2326 Chapter 7.4: Serializing Instructions 2327 2328The SPARC Architecture Manual, Version 9 2329 Chapter 8: Memory Models 2330 Appendix D: Formal Specification of the Memory Models 2331 Appendix J: Programming with the Memory Models 2332 2333UltraSPARC Programmer Reference Manual 2334 Chapter 5: Memory Accesses and Cacheability 2335 Chapter 15: Sparc-V9 Memory Models 2336 2337UltraSPARC III Cu User's Manual 2338 Chapter 9: Memory Models 2339 2340UltraSPARC IIIi Processor User's Manual 2341 Chapter 8: Memory Models 2342 2343UltraSPARC Architecture 2005 2344 Chapter 9: Memory 2345 Appendix D: Formal Specifications of the Memory Models 2346 2347UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005 2348 Chapter 8: Memory Models 2349 Appendix F: Caches and Cache Coherency 2350 2351Solaris Internals, Core Kernel Architecture, p63-68: 2352 Chapter 3.3: Hardware Considerations for Locks and 2353 Synchronization 2354 2355Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching 2356for Kernel Programmers: 2357 Chapter 13: Other Memory Models 2358 2359Intel Itanium Architecture Software Developer's Manual: Volume 1: 2360 Section 2.6: Speculation 2361 Section 4.4: Memory Access 2362