1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_runtime_pm_disable_interrupts 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_runtime_pm_enable_interrupts 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 119 :internal: 120 121Asynchronous Page Flip 122---------------------- 123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127Output Probing 128-------------- 129 130This section covers output probing and related infrastructure like the 131hotplug interrupt storm detection and mitigation code. Note that the 132i915 driver still uses most of the common DRM helper code for output 133probing, so those sections fully apply. 134 135Hotplug 136------- 137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144High Definition Audio 145--------------------- 146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153.. kernel-doc:: include/drm/i915_component.h 154 :internal: 155 156Intel HDMI LPE Audio Support 157---------------------------- 158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165Panel Self Refresh PSR (PSR/SRD) 166-------------------------------- 167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174Frame Buffer Compression (FBC) 175------------------------------ 176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183Display Refresh Rate Switching (DRRS) 184------------------------------------- 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :functions: intel_drrs_enable 191 192.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 193 :functions: intel_drrs_disable 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 196 :functions: intel_drrs_invalidate 197 198.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 199 :functions: intel_drrs_flush 200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 202 :functions: intel_drrs_init 203 204DPIO 205---- 206 207.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 208 :doc: DPIO 209 210DMC Firmware Support 211-------------------- 212 213.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 214 :doc: DMC Firmware Support 215 216.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 217 :internal: 218 219Video BIOS Table (VBT) 220---------------------- 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 223 :doc: Video BIOS Table (VBT) 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 226 :internal: 227 228.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 229 :internal: 230 231Display clocks 232-------------- 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 235 :doc: CDCLK / RAWCLK 236 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 238 :internal: 239 240Display PLLs 241------------ 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 244 :doc: Display PLLs 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 247 :internal: 248 249.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 250 :internal: 251 252Display State Buffer 253-------------------- 254 255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 256 :doc: DSB 257 258.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 259 :internal: 260 261Memory Management and Command Submission 262======================================== 263 264This sections covers all things related to the GEM implementation in the 265i915 driver. 266 267Intel GPU Basics 268---------------- 269 270An Intel GPU has multiple engines. There are several engine types. 271 272- RCS engine is for rendering 3D and performing compute, this is named 273 `I915_EXEC_RENDER` in user space. 274- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user 275 space. 276- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` 277 in user space 278- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user 279 space. 280- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; 281 instead it is to be used by user space to specify a default rendering 282 engine (for 3D) that may or may not be the same as RCS. 283 284The Intel GPU family is a family of integrated GPU's using Unified 285Memory Access. For having the GPU "do work", user space will feed the 286GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 287or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 288instruct the GPU to perform work (for example rendering) and that work 289needs memory from which to read and memory to which to write. All memory 290is encapsulated within GEM buffer objects (usually created with the ioctl 291`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 292to create will also list all GEM buffer objects that the batchbuffer reads 293and/or writes. For implementation details of memory management see 294`GEM BO Management Implementation Details`_. 295 296The i915 driver allows user space to create a context via the ioctl 297`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 298integer. Such a context should be viewed by user-space as -loosely- 299analogous to the idea of a CPU process of an operating system. The i915 300driver guarantees that commands issued to a fixed context are to be 301executed so that writes of a previously issued command are seen by 302reads of following commands. Actions issued between different contexts 303(even if from the same file descriptor) are NOT given that guarantee 304and the only way to synchronize across contexts (even from the same 305file descriptor) is through the use of fences. At least as far back as 306Gen4, also have that a context carries with it a GPU HW context; 307the HW context is essentially (most of atleast) the state of a GPU. 308In addition to the ordering guarantees, the kernel will restore GPU 309state via HW context when commands are issued to a context, this saves 310user space the need to restore (most of atleast) the GPU state at the 311start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 312work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 313to identify what context to use with the command. 314 315The GPU has its own memory management and address space. The kernel 316driver maintains the memory translation table for the GPU. For older 317GPUs (i.e. those before Gen8), there is a single global such translation 318table, a global Graphics Translation Table (GTT). For newer generation 319GPUs each context has its own translation table, called Per-Process 320Graphics Translation Table (PPGTT). Of important note, is that although 321PPGTT is named per-process it is actually per context. When user space 322submits a batchbuffer, the kernel walks the list of GEM buffer objects 323used by the batchbuffer and guarantees that not only is the memory of 324each such GEM buffer object resident but it is also present in the 325(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 326then it is given an address. Two consequences of this are: the kernel 327needs to edit the batchbuffer submitted to write the correct value of 328the GPU address when a GEM BO is assigned a GPU address and the kernel 329might evict a different GEM BO from the (PP)GTT to make address room 330for another GEM BO. Consequently, the ioctls submitting a batchbuffer 331for execution also include a list of all locations within buffers that 332refer to GPU-addresses so that the kernel can edit the buffer correctly. 333This process is dubbed relocation. 334 335Locking Guidelines 336------------------ 337 338.. note:: 339 This is a description of how the locking should be after 340 refactoring is done. Does not necessarily reflect what the locking 341 looks like while WIP. 342 343#. All locking rules and interface contracts with cross-driver interfaces 344 (dma-buf, dma_fence) need to be followed. 345 346#. No struct_mutex anywhere in the code 347 348#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 349 is to be hoisted at highest level and passed down within i915_gem_ctx 350 in the call chain 351 352#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 353 system memory allocations are not allowed 354 355 * Enforce this by priming lockdep (with fs_reclaim). If we 356 allocate memory while holding these looks we get a rehash 357 of the shrinker vs. struct_mutex saga, and that would be 358 real bad. 359 360#. Do not nest different lru/memory manager locks within each other. 361 Take them in turn to update memory allocations, relying on the object’s 362 dma_resv ww_mutex to serialize against other operations. 363 364#. The suggestion for lru/memory managers locks is that they are small 365 enough to be spinlocks. 366 367#. All features need to come with exhaustive kernel selftests and/or 368 IGT tests when appropriate 369 370#. All LMEM uAPI paths need to be fully restartable (_interruptible() 371 for all locks/waits/sleeps) 372 373 * Error handling validation through signal injection. 374 Still the best strategy we have for validating GEM uAPI 375 corner cases. 376 Must be excessively used in the IGT, and we need to check 377 that we really have full path coverage of all error cases. 378 379 * -EDEADLK handling with ww_mutex 380 381GEM BO Management Implementation Details 382---------------------------------------- 383 384.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 385 :doc: Virtual Memory Address 386 387Buffer Object Eviction 388---------------------- 389 390This section documents the interface functions for evicting buffer 391objects to make space available in the virtual gpu address spaces. Note 392that this is mostly orthogonal to shrinking buffer objects caches, which 393has the goal to make main memory (shared with the gpu through the 394unified memory architecture) available. 395 396.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 397 :internal: 398 399Buffer Object Memory Shrinking 400------------------------------ 401 402This section documents the interface function for shrinking memory usage 403of buffer object caches. Shrinking is used to make main memory 404available. Note that this is mostly orthogonal to evicting buffer 405objects, which has the goal to make space in gpu virtual address spaces. 406 407.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 408 :internal: 409 410Batchbuffer Parsing 411------------------- 412 413.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 414 :doc: batch buffer command parser 415 416.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 417 :internal: 418 419User Batchbuffer Execution 420-------------------------- 421 422.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 423 424.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 425 :doc: User command execution 426 427Scheduling 428---------- 429.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 430 :functions: i915_sched_engine 431 432Logical Rings, Logical Ring Contexts and Execlists 433-------------------------------------------------- 434 435.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 436 :doc: Logical Rings, Logical Ring Contexts and Execlists 437 438Global GTT views 439---------------- 440 441.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 442 :doc: Global GTT views 443 444.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 445 :internal: 446 447GTT Fences and Swizzling 448------------------------ 449 450.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 451 :internal: 452 453Global GTT Fence Handling 454~~~~~~~~~~~~~~~~~~~~~~~~~ 455 456.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 457 :doc: fence register handling 458 459Hardware Tiling and Swizzling Details 460~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 461 462.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 463 :doc: tiling swizzling details 464 465Object Tiling IOCTLs 466-------------------- 467 468.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 469 :internal: 470 471.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 472 :doc: buffer object tiling 473 474Protected Objects 475----------------- 476 477.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 478 :doc: PXP 479 480.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 481 482Microcontrollers 483================ 484 485Starting from gen9, three microcontrollers are available on the HW: the 486graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 487display microcontroller (DMC). The driver is responsible for loading the 488firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 489to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 490 491WOPCM 492----- 493 494WOPCM Layout 495~~~~~~~~~~~~ 496 497.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c 498 :doc: WOPCM Layout 499 500GuC 501--- 502 503.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 504 :doc: GuC 505 506.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 507 508GuC Firmware Layout 509~~~~~~~~~~~~~~~~~~~ 510 511.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 512 :doc: Firmware Layout 513 514GuC Memory Management 515~~~~~~~~~~~~~~~~~~~~~ 516 517.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 518 :doc: GuC Memory Management 519.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 520 :functions: intel_guc_allocate_vma 521 522 523GuC-specific firmware loader 524~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 525 526.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 527 :internal: 528 529GuC-based command submission 530~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 531 532.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 533 :doc: GuC-based command submission 534 535GuC ABI 536~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 537 538.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 539.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 540.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 541.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 542 543HuC 544--- 545.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 546 :doc: HuC 547.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 548 :functions: intel_huc_auth 549 550HuC Memory Management 551~~~~~~~~~~~~~~~~~~~~~ 552 553.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 554 :doc: HuC Memory Management 555 556HuC Firmware Layout 557~~~~~~~~~~~~~~~~~~~ 558The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 559 560DMC 561--- 562See `DMC Firmware Support`_ 563 564Tracing 565======= 566 567This sections covers all things related to the tracepoints implemented 568in the i915 driver. 569 570i915_ppgtt_create and i915_ppgtt_release 571---------------------------------------- 572 573.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 574 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 575 576i915_context_create and i915_context_free 577----------------------------------------- 578 579.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 580 :doc: i915_context_create and i915_context_free tracepoints 581 582Perf 583==== 584 585Overview 586-------- 587.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 588 :doc: i915 Perf Overview 589 590Comparison with Core Perf 591------------------------- 592.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 593 :doc: i915 Perf History and Comparison with Core Perf 594 595i915 Driver Entry Points 596------------------------ 597 598This section covers the entrypoints exported outside of i915_perf.c to 599integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 600 601.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 602 :functions: i915_perf_init 603.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 604 :functions: i915_perf_fini 605.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 606 :functions: i915_perf_register 607.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 608 :functions: i915_perf_unregister 609.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 610 :functions: i915_perf_open_ioctl 611.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 612 :functions: i915_perf_release 613.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 614 :functions: i915_perf_add_config_ioctl 615.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 616 :functions: i915_perf_remove_config_ioctl 617 618i915 Perf Stream 619---------------- 620 621This section covers the stream-semantics-agnostic structures and functions 622for representing an i915 perf stream FD and associated file operations. 623 624.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 625 :functions: i915_perf_stream 626.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 627 :functions: i915_perf_stream_ops 628 629.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 630 :functions: read_properties_unlocked 631.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 632 :functions: i915_perf_open_ioctl_locked 633.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 634 :functions: i915_perf_destroy_locked 635.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 636 :functions: i915_perf_read 637.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 638 :functions: i915_perf_ioctl 639.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 640 :functions: i915_perf_enable_locked 641.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 642 :functions: i915_perf_disable_locked 643.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 644 :functions: i915_perf_poll 645.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 646 :functions: i915_perf_poll_locked 647 648i915 Perf Observation Architecture Stream 649----------------------------------------- 650 651.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 652 :functions: i915_oa_ops 653 654.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 655 :functions: i915_oa_stream_init 656.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 657 :functions: i915_oa_read 658.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 659 :functions: i915_oa_stream_enable 660.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 661 :functions: i915_oa_stream_disable 662.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 663 :functions: i915_oa_wait_unlocked 664.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 665 :functions: i915_oa_poll_wait 666 667Other i915 Perf Internals 668------------------------- 669 670This section simply includes all other currently documented i915 perf internals, 671in no particular order, but may include some more minor utilities or platform 672specific details than found in the more high-level sections. 673 674.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 675 :internal: 676 :no-identifiers: 677 i915_perf_init 678 i915_perf_fini 679 i915_perf_register 680 i915_perf_unregister 681 i915_perf_open_ioctl 682 i915_perf_release 683 i915_perf_add_config_ioctl 684 i915_perf_remove_config_ioctl 685 read_properties_unlocked 686 i915_perf_open_ioctl_locked 687 i915_perf_destroy_locked 688 i915_perf_read i915_perf_ioctl 689 i915_perf_enable_locked 690 i915_perf_disable_locked 691 i915_perf_poll i915_perf_poll_locked 692 i915_oa_stream_init i915_oa_read 693 i915_oa_stream_enable 694 i915_oa_stream_disable 695 i915_oa_wait_unlocked 696 i915_oa_poll_wait 697 698Style 699===== 700 701The drm/i915 driver codebase has some style rules in addition to (and, in some 702cases, deviating from) the kernel coding style. 703 704Register macro definition style 705------------------------------- 706 707The style guide for ``i915_reg.h``. 708 709.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 710 :doc: The i915 register macro definition style guide 711