1=====================================
2MTD NAND Driver Programming Interface
3=====================================
4
5:Author: Thomas Gleixner
6
7Introduction
8============
9
10The generic NAND driver supports almost all NAND and AG-AND based chips
11and connects them to the Memory Technology Devices (MTD) subsystem of
12the Linux Kernel.
13
14This documentation is provided for developers who want to implement
15board drivers or filesystem drivers suitable for NAND devices.
16
17Known Bugs And Assumptions
18==========================
19
20None.
21
22Documentation hints
23===================
24
25The function and structure docs are autogenerated. Each function and
26struct member has a short description which is marked with an [XXX]
27identifier. The following chapters explain the meaning of those
28identifiers.
29
30Function identifiers [XXX]
31--------------------------
32
33The functions are marked with [XXX] identifiers in the short comment.
34The identifiers explain the usage and scope of the functions. Following
35identifiers are used:
36
37-  [MTD Interface]
38
39   These functions provide the interface to the MTD kernel API. They are
40   not replaceable and provide functionality which is complete hardware
41   independent.
42
43-  [NAND Interface]
44
45   These functions are exported and provide the interface to the NAND
46   kernel API.
47
48-  [GENERIC]
49
50   Generic functions are not replaceable and provide functionality which
51   is complete hardware independent.
52
53-  [DEFAULT]
54
55   Default functions provide hardware related functionality which is
56   suitable for most of the implementations. These functions can be
57   replaced by the board driver if necessary. Those functions are called
58   via pointers in the NAND chip description structure. The board driver
59   can set the functions which should be replaced by board dependent
60   functions before calling nand_scan(). If the function pointer is
61   NULL on entry to nand_scan() then the pointer is set to the default
62   function which is suitable for the detected chip type.
63
64Struct member identifiers [XXX]
65-------------------------------
66
67The struct members are marked with [XXX] identifiers in the comment. The
68identifiers explain the usage and scope of the members. Following
69identifiers are used:
70
71-  [INTERN]
72
73   These members are for NAND driver internal use only and must not be
74   modified. Most of these values are calculated from the chip geometry
75   information which is evaluated during nand_scan().
76
77-  [REPLACEABLE]
78
79   Replaceable members hold hardware related functions which can be
80   provided by the board driver. The board driver can set the functions
81   which should be replaced by board dependent functions before calling
82   nand_scan(). If the function pointer is NULL on entry to
83   nand_scan() then the pointer is set to the default function which is
84   suitable for the detected chip type.
85
86-  [BOARDSPECIFIC]
87
88   Board specific members hold hardware related information which must
89   be provided by the board driver. The board driver must set the
90   function pointers and datafields before calling nand_scan().
91
92-  [OPTIONAL]
93
94   Optional members can hold information relevant for the board driver.
95   The generic NAND driver code does not use this information.
96
97Basic board driver
98==================
99
100For most boards it will be sufficient to provide just the basic
101functions and fill out some really board dependent members in the nand
102chip description structure.
103
104Basic defines
105-------------
106
107At least you have to provide a nand_chip structure and a storage for
108the ioremap'ed chip address. You can allocate the nand_chip structure
109using kmalloc or you can allocate it statically. The NAND chip structure
110embeds an mtd structure which will be registered to the MTD subsystem.
111You can extract a pointer to the mtd structure from a nand_chip pointer
112using the nand_to_mtd() helper.
113
114Kmalloc based example
115
116::
117
118    static struct mtd_info *board_mtd;
119    static void __iomem *baseaddr;
120
121
122Static example
123
124::
125
126    static struct nand_chip board_chip;
127    static void __iomem *baseaddr;
128
129
130Partition defines
131-----------------
132
133If you want to divide your device into partitions, then define a
134partitioning scheme suitable to your board.
135
136::
137
138    #define NUM_PARTITIONS 2
139    static struct mtd_partition partition_info[] = {
140        { .name = "Flash partition 1",
141          .offset =  0,
142          .size =    8 * 1024 * 1024 },
143        { .name = "Flash partition 2",
144          .offset =  MTDPART_OFS_NEXT,
145          .size =    MTDPART_SIZ_FULL },
146    };
147
148
149Hardware control function
150-------------------------
151
152The hardware control function provides access to the control pins of the
153NAND chip(s). The access can be done by GPIO pins or by address lines.
154If you use address lines, make sure that the timing requirements are
155met.
156
157*GPIO based example*
158
159::
160
161    static void board_hwcontrol(struct mtd_info *mtd, int cmd)
162    {
163        switch(cmd){
164            case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
165            case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
166            case NAND_CTL_SETALE: /* Set ALE pin high */ break;
167            case NAND_CTL_CLRALE: /* Set ALE pin low */ break;
168            case NAND_CTL_SETNCE: /* Set nCE pin low */ break;
169            case NAND_CTL_CLRNCE: /* Set nCE pin high */ break;
170        }
171    }
172
173
174*Address lines based example.* It's assumed that the nCE pin is driven
175by a chip select decoder.
176
177::
178
179    static void board_hwcontrol(struct mtd_info *mtd, int cmd)
180    {
181        struct nand_chip *this = mtd_to_nand(mtd);
182        switch(cmd){
183            case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT;  break;
184            case NAND_CTL_CLRCLE: this->IO_ADDR_W &= ~CLE_ADRR_BIT; break;
185            case NAND_CTL_SETALE: this->IO_ADDR_W |= ALE_ADRR_BIT;  break;
186            case NAND_CTL_CLRALE: this->IO_ADDR_W &= ~ALE_ADRR_BIT; break;
187        }
188    }
189
190
191Device ready function
192---------------------
193
194If the hardware interface has the ready busy pin of the NAND chip
195connected to a GPIO or other accessible I/O pin, this function is used
196to read back the state of the pin. The function has no arguments and
197should return 0, if the device is busy (R/B pin is low) and 1, if the
198device is ready (R/B pin is high). If the hardware interface does not
199give access to the ready busy pin, then the function must not be defined
200and the function pointer this->dev_ready is set to NULL.
201
202Init function
203-------------
204
205The init function allocates memory and sets up all the board specific
206parameters and function pointers. When everything is set up nand_scan()
207is called. This function tries to detect and identify then chip. If a
208chip is found all the internal data fields are initialized accordingly.
209The structure(s) have to be zeroed out first and then filled with the
210necessary information about the device.
211
212::
213
214    static int __init board_init (void)
215    {
216        struct nand_chip *this;
217        int err = 0;
218
219        /* Allocate memory for MTD device structure and private data */
220        this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
221        if (!this) {
222            printk ("Unable to allocate NAND MTD device structure.\n");
223            err = -ENOMEM;
224            goto out;
225        }
226
227        board_mtd = nand_to_mtd(this);
228
229        /* map physical address */
230        baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024);
231        if (!baseaddr) {
232            printk("Ioremap to access NAND chip failed\n");
233            err = -EIO;
234            goto out_mtd;
235        }
236
237        /* Set address of NAND IO lines */
238        this->IO_ADDR_R = baseaddr;
239        this->IO_ADDR_W = baseaddr;
240        /* Reference hardware control function */
241        this->hwcontrol = board_hwcontrol;
242        /* Set command delay time, see datasheet for correct value */
243        this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
244        /* Assign the device ready function, if available */
245        this->dev_ready = board_dev_ready;
246        this->eccmode = NAND_ECC_SOFT;
247
248        /* Scan to find existence of the device */
249        if (nand_scan (board_mtd, 1)) {
250            err = -ENXIO;
251            goto out_ior;
252        }
253
254        add_mtd_partitions(board_mtd, partition_info, NUM_PARTITIONS);
255        goto out;
256
257    out_ior:
258        iounmap(baseaddr);
259    out_mtd:
260        kfree (this);
261    out:
262        return err;
263    }
264    module_init(board_init);
265
266
267Exit function
268-------------
269
270The exit function is only necessary if the driver is compiled as a
271module. It releases all resources which are held by the chip driver and
272unregisters the partitions in the MTD layer.
273
274::
275
276    #ifdef MODULE
277    static void __exit board_cleanup (void)
278    {
279        /* Release resources, unregister device */
280        nand_release (board_mtd);
281
282        /* unmap physical address */
283        iounmap(baseaddr);
284
285        /* Free the MTD device structure */
286        kfree (mtd_to_nand(board_mtd));
287    }
288    module_exit(board_cleanup);
289    #endif
290
291
292Advanced board driver functions
293===============================
294
295This chapter describes the advanced functionality of the NAND driver.
296For a list of functions which can be overridden by the board driver see
297the documentation of the nand_chip structure.
298
299Multiple chip control
300---------------------
301
302The nand driver can control chip arrays. Therefore the board driver must
303provide an own select_chip function. This function must (de)select the
304requested chip. The function pointer in the nand_chip structure must be
305set before calling nand_scan(). The maxchip parameter of nand_scan()
306defines the maximum number of chips to scan for. Make sure that the
307select_chip function can handle the requested number of chips.
308
309The nand driver concatenates the chips to one virtual chip and provides
310this virtual chip to the MTD layer.
311
312*Note: The driver can only handle linear chip arrays of equally sized
313chips. There is no support for parallel arrays which extend the
314buswidth.*
315
316*GPIO based example*
317
318::
319
320    static void board_select_chip (struct mtd_info *mtd, int chip)
321    {
322        /* Deselect all chips, set all nCE pins high */
323        GPIO(BOARD_NAND_NCE) |= 0xff;
324        if (chip >= 0)
325            GPIO(BOARD_NAND_NCE) &= ~ (1 << chip);
326    }
327
328
329*Address lines based example.* Its assumed that the nCE pins are
330connected to an address decoder.
331
332::
333
334    static void board_select_chip (struct mtd_info *mtd, int chip)
335    {
336        struct nand_chip *this = mtd_to_nand(mtd);
337
338        /* Deselect all chips */
339        this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
340        this->IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
341        switch (chip) {
342        case 0:
343            this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
344            this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
345            break;
346        ....
347        case n:
348            this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
349            this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
350            break;
351        }
352    }
353
354
355Hardware ECC support
356--------------------
357
358Functions and constants
359~~~~~~~~~~~~~~~~~~~~~~~
360
361The nand driver supports three different types of hardware ECC.
362
363-  NAND_ECC_HW3_256
364
365   Hardware ECC generator providing 3 bytes ECC per 256 byte.
366
367-  NAND_ECC_HW3_512
368
369   Hardware ECC generator providing 3 bytes ECC per 512 byte.
370
371-  NAND_ECC_HW6_512
372
373   Hardware ECC generator providing 6 bytes ECC per 512 byte.
374
375-  NAND_ECC_HW8_512
376
377   Hardware ECC generator providing 6 bytes ECC per 512 byte.
378
379If your hardware generator has a different functionality add it at the
380appropriate place in nand_base.c
381
382The board driver must provide following functions:
383
384-  enable_hwecc
385
386   This function is called before reading / writing to the chip. Reset
387   or initialize the hardware generator in this function. The function
388   is called with an argument which let you distinguish between read and
389   write operations.
390
391-  calculate_ecc
392
393   This function is called after read / write from / to the chip.
394   Transfer the ECC from the hardware to the buffer. If the option
395   NAND_HWECC_SYNDROME is set then the function is only called on
396   write. See below.
397
398-  correct_data
399
400   In case of an ECC error this function is called for error detection
401   and correction. Return 1 respectively 2 in case the error can be
402   corrected. If the error is not correctable return -1. If your
403   hardware generator matches the default algorithm of the nand_ecc
404   software generator then use the correction function provided by
405   nand_ecc instead of implementing duplicated code.
406
407Hardware ECC with syndrome calculation
408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
409
410Many hardware ECC implementations provide Reed-Solomon codes and
411calculate an error syndrome on read. The syndrome must be converted to a
412standard Reed-Solomon syndrome before calling the error correction code
413in the generic Reed-Solomon library.
414
415The ECC bytes must be placed immediately after the data bytes in order
416to make the syndrome generator work. This is contrary to the usual
417layout used by software ECC. The separation of data and out of band area
418is not longer possible. The nand driver code handles this layout and the
419remaining free bytes in the oob area are managed by the autoplacement
420code. Provide a matching oob-layout in this case. See rts_from4.c and
421diskonchip.c for implementation reference. In those cases we must also
422use bad block tables on FLASH, because the ECC layout is interfering
423with the bad block marker positions. See bad block table support for
424details.
425
426Bad block table support
427-----------------------
428
429Most NAND chips mark the bad blocks at a defined position in the spare
430area. Those blocks must not be erased under any circumstances as the bad
431block information would be lost. It is possible to check the bad block
432mark each time when the blocks are accessed by reading the spare area of
433the first page in the block. This is time consuming so a bad block table
434is used.
435
436The nand driver supports various types of bad block tables.
437
438-  Per device
439
440   The bad block table contains all bad block information of the device
441   which can consist of multiple chips.
442
443-  Per chip
444
445   A bad block table is used per chip and contains the bad block
446   information for this particular chip.
447
448-  Fixed offset
449
450   The bad block table is located at a fixed offset in the chip
451   (device). This applies to various DiskOnChip devices.
452
453-  Automatic placed
454
455   The bad block table is automatically placed and detected either at
456   the end or at the beginning of a chip (device)
457
458-  Mirrored tables
459
460   The bad block table is mirrored on the chip (device) to allow updates
461   of the bad block table without data loss.
462
463nand_scan() calls the function nand_default_bbt().
464nand_default_bbt() selects appropriate default bad block table
465descriptors depending on the chip information which was retrieved by
466nand_scan().
467
468The standard policy is scanning the device for bad blocks and build a
469ram based bad block table which allows faster access than always
470checking the bad block information on the flash chip itself.
471
472Flash based tables
473~~~~~~~~~~~~~~~~~~
474
475It may be desired or necessary to keep a bad block table in FLASH. For
476AG-AND chips this is mandatory, as they have no factory marked bad
477blocks. They have factory marked good blocks. The marker pattern is
478erased when the block is erased to be reused. So in case of powerloss
479before writing the pattern back to the chip this block would be lost and
480added to the bad blocks. Therefore we scan the chip(s) when we detect
481them the first time for good blocks and store this information in a bad
482block table before erasing any of the blocks.
483
484The blocks in which the tables are stored are protected against
485accidental access by marking them bad in the memory bad block table. The
486bad block table management functions are allowed to circumvent this
487protection.
488
489The simplest way to activate the FLASH based bad block table support is
490to set the option NAND_BBT_USE_FLASH in the bbt_option field of the
491nand chip structure before calling nand_scan(). For AG-AND chips is
492this done by default. This activates the default FLASH based bad block
493table functionality of the NAND driver. The default bad block table
494options are
495
496-  Store bad block table per chip
497
498-  Use 2 bits per block
499
500-  Automatic placement at the end of the chip
501
502-  Use mirrored tables with version numbers
503
504-  Reserve 4 blocks at the end of the chip
505
506User defined tables
507~~~~~~~~~~~~~~~~~~~
508
509User defined tables are created by filling out a nand_bbt_descr
510structure and storing the pointer in the nand_chip structure member
511bbt_td before calling nand_scan(). If a mirror table is necessary a
512second structure must be created and a pointer to this structure must be
513stored in bbt_md inside the nand_chip structure. If the bbt_md member
514is set to NULL then only the main table is used and no scan for the
515mirrored table is performed.
516
517The most important field in the nand_bbt_descr structure is the
518options field. The options define most of the table properties. Use the
519predefined constants from rawnand.h to define the options.
520
521-  Number of bits per block
522
523   The supported number of bits is 1, 2, 4, 8.
524
525-  Table per chip
526
527   Setting the constant NAND_BBT_PERCHIP selects that a bad block
528   table is managed for each chip in a chip array. If this option is not
529   set then a per device bad block table is used.
530
531-  Table location is absolute
532
533   Use the option constant NAND_BBT_ABSPAGE and define the absolute
534   page number where the bad block table starts in the field pages. If
535   you have selected bad block tables per chip and you have a multi chip
536   array then the start page must be given for each chip in the chip
537   array. Note: there is no scan for a table ident pattern performed, so
538   the fields pattern, veroffs, offs, len can be left uninitialized
539
540-  Table location is automatically detected
541
542   The table can either be located in the first or the last good blocks
543   of the chip (device). Set NAND_BBT_LASTBLOCK to place the bad block
544   table at the end of the chip (device). The bad block tables are
545   marked and identified by a pattern which is stored in the spare area
546   of the first page in the block which holds the bad block table. Store
547   a pointer to the pattern in the pattern field. Further the length of
548   the pattern has to be stored in len and the offset in the spare area
549   must be given in the offs member of the nand_bbt_descr structure.
550   For mirrored bad block tables different patterns are mandatory.
551
552-  Table creation
553
554   Set the option NAND_BBT_CREATE to enable the table creation if no
555   table can be found during the scan. Usually this is done only once if
556   a new chip is found.
557
558-  Table write support
559
560   Set the option NAND_BBT_WRITE to enable the table write support.
561   This allows the update of the bad block table(s) in case a block has
562   to be marked bad due to wear. The MTD interface function
563   block_markbad is calling the update function of the bad block table.
564   If the write support is enabled then the table is updated on FLASH.
565
566   Note: Write support should only be enabled for mirrored tables with
567   version control.
568
569-  Table version control
570
571   Set the option NAND_BBT_VERSION to enable the table version
572   control. It's highly recommended to enable this for mirrored tables
573   with write support. It makes sure that the risk of losing the bad
574   block table information is reduced to the loss of the information
575   about the one worn out block which should be marked bad. The version
576   is stored in 4 consecutive bytes in the spare area of the device. The
577   position of the version number is defined by the member veroffs in
578   the bad block table descriptor.
579
580-  Save block contents on write
581
582   In case that the block which holds the bad block table does contain
583   other useful information, set the option NAND_BBT_SAVECONTENT. When
584   the bad block table is written then the whole block is read the bad
585   block table is updated and the block is erased and everything is
586   written back. If this option is not set only the bad block table is
587   written and everything else in the block is ignored and erased.
588
589-  Number of reserved blocks
590
591   For automatic placement some blocks must be reserved for bad block
592   table storage. The number of reserved blocks is defined in the
593   maxblocks member of the bad block table description structure.
594   Reserving 4 blocks for mirrored tables should be a reasonable number.
595   This also limits the number of blocks which are scanned for the bad
596   block table ident pattern.
597
598Spare area (auto)placement
599--------------------------
600
601The nand driver implements different possibilities for placement of
602filesystem data in the spare area,
603
604-  Placement defined by fs driver
605
606-  Automatic placement
607
608The default placement function is automatic placement. The nand driver
609has built in default placement schemes for the various chiptypes. If due
610to hardware ECC functionality the default placement does not fit then
611the board driver can provide a own placement scheme.
612
613File system drivers can provide a own placement scheme which is used
614instead of the default placement scheme.
615
616Placement schemes are defined by a nand_oobinfo structure
617
618::
619
620    struct nand_oobinfo {
621        int useecc;
622        int eccbytes;
623        int eccpos[24];
624        int oobfree[8][2];
625    };
626
627
628-  useecc
629
630   The useecc member controls the ecc and placement function. The header
631   file include/mtd/mtd-abi.h contains constants to select ecc and
632   placement. MTD_NANDECC_OFF switches off the ecc complete. This is
633   not recommended and available for testing and diagnosis only.
634   MTD_NANDECC_PLACE selects caller defined placement,
635   MTD_NANDECC_AUTOPLACE selects automatic placement.
636
637-  eccbytes
638
639   The eccbytes member defines the number of ecc bytes per page.
640
641-  eccpos
642
643   The eccpos array holds the byte offsets in the spare area where the
644   ecc codes are placed.
645
646-  oobfree
647
648   The oobfree array defines the areas in the spare area which can be
649   used for automatic placement. The information is given in the format
650   {offset, size}. offset defines the start of the usable area, size the
651   length in bytes. More than one area can be defined. The list is
652   terminated by an {0, 0} entry.
653
654Placement defined by fs driver
655~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
656
657The calling function provides a pointer to a nand_oobinfo structure
658which defines the ecc placement. For writes the caller must provide a
659spare area buffer along with the data buffer. The spare area buffer size
660is (number of pages) \* (size of spare area). For reads the buffer size
661is (number of pages) \* ((size of spare area) + (number of ecc steps per
662page) \* sizeof (int)). The driver stores the result of the ecc check
663for each tuple in the spare buffer. The storage sequence is::
664
665	<spare data page 0><ecc result 0>...<ecc result n>
666
667	...
668
669	<spare data page n><ecc result 0>...<ecc result n>
670
671This is a legacy mode used by YAFFS1.
672
673If the spare area buffer is NULL then only the ECC placement is done
674according to the given scheme in the nand_oobinfo structure.
675
676Automatic placement
677~~~~~~~~~~~~~~~~~~~
678
679Automatic placement uses the built in defaults to place the ecc bytes in
680the spare area. If filesystem data have to be stored / read into the
681spare area then the calling function must provide a buffer. The buffer
682size per page is determined by the oobfree array in the nand_oobinfo
683structure.
684
685If the spare area buffer is NULL then only the ECC placement is done
686according to the default builtin scheme.
687
688Spare area autoplacement default schemes
689----------------------------------------
690
691256 byte pagesize
692~~~~~~~~~~~~~~~~~
693
694======== ================== ===================================================
695Offset   Content            Comment
696======== ================== ===================================================
6970x00     ECC byte 0         Error correction code byte 0
6980x01     ECC byte 1         Error correction code byte 1
6990x02     ECC byte 2         Error correction code byte 2
7000x03     Autoplace 0
7010x04     Autoplace 1
7020x05     Bad block marker   If any bit in this byte is zero, then this
703			    block is bad. This applies only to the first
704			    page in a block. In the remaining pages this
705			    byte is reserved
7060x06     Autoplace 2
7070x07     Autoplace 3
708======== ================== ===================================================
709
710512 byte pagesize
711~~~~~~~~~~~~~~~~~
712
713
714============= ================== ==============================================
715Offset        Content            Comment
716============= ================== ==============================================
7170x00          ECC byte 0         Error correction code byte 0 of the lower
718				 256 Byte data in this page
7190x01          ECC byte 1         Error correction code byte 1 of the lower
720				 256 Bytes of data in this page
7210x02          ECC byte 2         Error correction code byte 2 of the lower
722				 256 Bytes of data in this page
7230x03          ECC byte 3         Error correction code byte 0 of the upper
724				 256 Bytes of data in this page
7250x04          reserved           reserved
7260x05          Bad block marker   If any bit in this byte is zero, then this
727				 block is bad. This applies only to the first
728				 page in a block. In the remaining pages this
729				 byte is reserved
7300x06          ECC byte 4         Error correction code byte 1 of the upper
731				 256 Bytes of data in this page
7320x07          ECC byte 5         Error correction code byte 2 of the upper
733				 256 Bytes of data in this page
7340x08 - 0x0F   Autoplace 0 - 7
735============= ================== ==============================================
736
7372048 byte pagesize
738~~~~~~~~~~~~~~~~~~
739
740=========== ================== ================================================
741Offset      Content            Comment
742=========== ================== ================================================
7430x00        Bad block marker   If any bit in this byte is zero, then this block
744			       is bad. This applies only to the first page in a
745			       block. In the remaining pages this byte is
746			       reserved
7470x01        Reserved           Reserved
7480x02-0x27   Autoplace 0 - 37
7490x28        ECC byte 0         Error correction code byte 0 of the first
750			       256 Byte data in this page
7510x29        ECC byte 1         Error correction code byte 1 of the first
752			       256 Bytes of data in this page
7530x2A        ECC byte 2         Error correction code byte 2 of the first
754			       256 Bytes data in this page
7550x2B        ECC byte 3         Error correction code byte 0 of the second
756			       256 Bytes of data in this page
7570x2C        ECC byte 4         Error correction code byte 1 of the second
758			       256 Bytes of data in this page
7590x2D        ECC byte 5         Error correction code byte 2 of the second
760			       256 Bytes of data in this page
7610x2E        ECC byte 6         Error correction code byte 0 of the third
762			       256 Bytes of data in this page
7630x2F        ECC byte 7         Error correction code byte 1 of the third
764			       256 Bytes of data in this page
7650x30        ECC byte 8         Error correction code byte 2 of the third
766			       256 Bytes of data in this page
7670x31        ECC byte 9         Error correction code byte 0 of the fourth
768			       256 Bytes of data in this page
7690x32        ECC byte 10        Error correction code byte 1 of the fourth
770			       256 Bytes of data in this page
7710x33        ECC byte 11        Error correction code byte 2 of the fourth
772			       256 Bytes of data in this page
7730x34        ECC byte 12        Error correction code byte 0 of the fifth
774			       256 Bytes of data in this page
7750x35        ECC byte 13        Error correction code byte 1 of the fifth
776			       256 Bytes of data in this page
7770x36        ECC byte 14        Error correction code byte 2 of the fifth
778			       256 Bytes of data in this page
7790x37        ECC byte 15        Error correction code byte 0 of the sixth
780			       256 Bytes of data in this page
7810x38        ECC byte 16        Error correction code byte 1 of the sixth
782			       256 Bytes of data in this page
7830x39        ECC byte 17        Error correction code byte 2 of the sixth
784			       256 Bytes of data in this page
7850x3A        ECC byte 18        Error correction code byte 0 of the seventh
786			       256 Bytes of data in this page
7870x3B        ECC byte 19        Error correction code byte 1 of the seventh
788			       256 Bytes of data in this page
7890x3C        ECC byte 20        Error correction code byte 2 of the seventh
790			       256 Bytes of data in this page
7910x3D        ECC byte 21        Error correction code byte 0 of the eighth
792			       256 Bytes of data in this page
7930x3E        ECC byte 22        Error correction code byte 1 of the eighth
794			       256 Bytes of data in this page
7950x3F        ECC byte 23        Error correction code byte 2 of the eighth
796			       256 Bytes of data in this page
797=========== ================== ================================================
798
799Filesystem support
800==================
801
802The NAND driver provides all necessary functions for a filesystem via
803the MTD interface.
804
805Filesystems must be aware of the NAND peculiarities and restrictions.
806One major restrictions of NAND Flash is, that you cannot write as often
807as you want to a page. The consecutive writes to a page, before erasing
808it again, are restricted to 1-3 writes, depending on the manufacturers
809specifications. This applies similar to the spare area.
810
811Therefore NAND aware filesystems must either write in page size chunks
812or hold a writebuffer to collect smaller writes until they sum up to
813pagesize. Available NAND aware filesystems: JFFS2, YAFFS.
814
815The spare area usage to store filesystem data is controlled by the spare
816area placement functionality which is described in one of the earlier
817chapters.
818
819Tools
820=====
821
822The MTD project provides a couple of helpful tools to handle NAND Flash.
823
824-  flasherase, flasheraseall: Erase and format FLASH partitions
825
826-  nandwrite: write filesystem images to NAND FLASH
827
828-  nanddump: dump the contents of a NAND FLASH partitions
829
830These tools are aware of the NAND restrictions. Please use those tools
831instead of complaining about errors which are caused by non NAND aware
832access methods.
833
834Constants
835=========
836
837This chapter describes the constants which might be relevant for a
838driver developer.
839
840Chip option constants
841---------------------
842
843Constants for chip id table
844~~~~~~~~~~~~~~~~~~~~~~~~~~~
845
846These constants are defined in rawnand.h. They are OR-ed together to
847describe the chip functionality::
848
849    /* Buswitdh is 16 bit */
850    #define NAND_BUSWIDTH_16    0x00000002
851    /* Device supports partial programming without padding */
852    #define NAND_NO_PADDING     0x00000004
853    /* Chip has cache program function */
854    #define NAND_CACHEPRG       0x00000008
855    /* Chip has copy back function */
856    #define NAND_COPYBACK       0x00000010
857    /* AND Chip which has 4 banks and a confusing page / block
858     * assignment. See Renesas datasheet for further information */
859    #define NAND_IS_AND     0x00000020
860    /* Chip has a array of 4 pages which can be read without
861     * additional ready /busy waits */
862    #define NAND_4PAGE_ARRAY    0x00000040
863
864
865Constants for runtime options
866~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
867
868These constants are defined in rawnand.h. They are OR-ed together to
869describe the functionality::
870
871    /* The hw ecc generator provides a syndrome instead a ecc value on read
872     * This can only work if we have the ecc bytes directly behind the
873     * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
874    #define NAND_HWECC_SYNDROME 0x00020000
875
876
877ECC selection constants
878-----------------------
879
880Use these constants to select the ECC algorithm::
881
882    /* No ECC. Usage is not recommended ! */
883    #define NAND_ECC_NONE       0
884    /* Software ECC 3 byte ECC per 256 Byte data */
885    #define NAND_ECC_SOFT       1
886    /* Hardware ECC 3 byte ECC per 256 Byte data */
887    #define NAND_ECC_HW3_256    2
888    /* Hardware ECC 3 byte ECC per 512 Byte data */
889    #define NAND_ECC_HW3_512    3
890    /* Hardware ECC 6 byte ECC per 512 Byte data */
891    #define NAND_ECC_HW6_512    4
892    /* Hardware ECC 6 byte ECC per 512 Byte data */
893    #define NAND_ECC_HW8_512    6
894
895
896Hardware control related constants
897----------------------------------
898
899These constants describe the requested hardware access function when the
900boardspecific hardware control function is called::
901
902    /* Select the chip by setting nCE to low */
903    #define NAND_CTL_SETNCE     1
904    /* Deselect the chip by setting nCE to high */
905    #define NAND_CTL_CLRNCE     2
906    /* Select the command latch by setting CLE to high */
907    #define NAND_CTL_SETCLE     3
908    /* Deselect the command latch by setting CLE to low */
909    #define NAND_CTL_CLRCLE     4
910    /* Select the address latch by setting ALE to high */
911    #define NAND_CTL_SETALE     5
912    /* Deselect the address latch by setting ALE to low */
913    #define NAND_CTL_CLRALE     6
914    /* Set write protection by setting WP to high. Not used! */
915    #define NAND_CTL_SETWP      7
916    /* Clear write protection by setting WP to low. Not used! */
917    #define NAND_CTL_CLRWP      8
918
919
920Bad block table related constants
921---------------------------------
922
923These constants describe the options used for bad block table
924descriptors::
925
926    /* Options for the bad block table descriptors */
927
928    /* The number of bits used per block in the bbt on the device */
929    #define NAND_BBT_NRBITS_MSK 0x0000000F
930    #define NAND_BBT_1BIT       0x00000001
931    #define NAND_BBT_2BIT       0x00000002
932    #define NAND_BBT_4BIT       0x00000004
933    #define NAND_BBT_8BIT       0x00000008
934    /* The bad block table is in the last good block of the device */
935    #define NAND_BBT_LASTBLOCK  0x00000010
936    /* The bbt is at the given page, else we must scan for the bbt */
937    #define NAND_BBT_ABSPAGE    0x00000020
938    /* bbt is stored per chip on multichip devices */
939    #define NAND_BBT_PERCHIP    0x00000080
940    /* bbt has a version counter at offset veroffs */
941    #define NAND_BBT_VERSION    0x00000100
942    /* Create a bbt if none axists */
943    #define NAND_BBT_CREATE     0x00000200
944    /* Write bbt if necessary */
945    #define NAND_BBT_WRITE      0x00001000
946    /* Read and write back block contents when writing bbt */
947    #define NAND_BBT_SAVECONTENT    0x00002000
948
949
950Structures
951==========
952
953This chapter contains the autogenerated documentation of the structures
954which are used in the NAND driver and might be relevant for a driver
955developer. Each struct member has a short description which is marked
956with an [XXX] identifier. See the chapter "Documentation hints" for an
957explanation.
958
959.. kernel-doc:: include/linux/mtd/rawnand.h
960   :internal:
961
962Public Functions Provided
963=========================
964
965This chapter contains the autogenerated documentation of the NAND kernel
966API functions which are exported. Each function has a short description
967which is marked with an [XXX] identifier. See the chapter "Documentation
968hints" for an explanation.
969
970.. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
971   :export:
972
973.. kernel-doc:: drivers/mtd/nand/raw/nand_ecc.c
974   :export:
975
976Internal Functions Provided
977===========================
978
979This chapter contains the autogenerated documentation of the NAND driver
980internal functions. Each function has a short description which is
981marked with an [XXX] identifier. See the chapter "Documentation hints"
982for an explanation. The functions marked with [DEFAULT] might be
983relevant for a board driver developer.
984
985.. kernel-doc:: drivers/mtd/nand/raw/nand_base.c
986   :internal:
987
988.. kernel-doc:: drivers/mtd/nand/raw/nand_bbt.c
989   :internal:
990
991Credits
992=======
993
994The following people have contributed to the NAND driver:
995
9961. Steven J. Hill\ sjhill@realitydiluted.com
997
9982. David Woodhouse\ dwmw2@infradead.org
999
10003. Thomas Gleixner\ tglx@linutronix.de
1001
1002A lot of users have provided bugfixes, improvements and helping hands
1003for testing. Thanks a lot.
1004
1005The following people have contributed to this document:
1006
10071. Thomas Gleixner\ tglx@linutronix.de
1008