13bf10ebcSSakari Ailus# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause 2*91f76941SSakari Ailus# Copyright (C) 2019--2020 Intel Corporation 33bf10ebcSSakari Ailus 43bf10ebcSSakari Ailus# register rflags 53bf10ebcSSakari Ailus# - f field LSB MSB rflags 63bf10ebcSSakari Ailus# - e enum value # after a field 73bf10ebcSSakari Ailus# - e enum value [LSB MSB] 83bf10ebcSSakari Ailus# - b bool bit 93bf10ebcSSakari Ailus# - l arg name min max elsize [discontig...] 103bf10ebcSSakari Ailus# 113bf10ebcSSakari Ailus# rflags 123bf10ebcSSakari Ailus# 8, 16, 32 register bits (default is 8) 133bf10ebcSSakari Ailus# v1.1 defined in version 1.1 143bf10ebcSSakari Ailus# f formula 153bf10ebcSSakari Ailus# float_ireal iReal or IEEE 754; 32 bits 163bf10ebcSSakari Ailus# ireal unsigned iReal 173bf10ebcSSakari Ailus 183bf10ebcSSakari Ailus# general status registers 193bf10ebcSSakari Ailusmodule_model_id 0x0000 16 203bf10ebcSSakari Ailusmodule_revision_number_major 0x0002 8 213bf10ebcSSakari Ailusframe_count 0x0005 8 223bf10ebcSSakari Ailuspixel_order 0x0006 8 233bf10ebcSSakari Ailus- e GRBG 0 243bf10ebcSSakari Ailus- e RGGB 1 253bf10ebcSSakari Ailus- e BGGR 2 263bf10ebcSSakari Ailus- e GBRG 3 273bf10ebcSSakari AilusMIPI_CCS_version 0x0007 8 283bf10ebcSSakari Ailus- e v1_0 0x10 293bf10ebcSSakari Ailus- e v1_1 0x11 303bf10ebcSSakari Ailus- f major 4 7 313bf10ebcSSakari Ailus- f minor 0 3 323bf10ebcSSakari Ailusdata_pedestal 0x0008 16 333bf10ebcSSakari Ailusmodule_manufacturer_id 0x000e 16 343bf10ebcSSakari Ailusmodule_revision_number_minor 0x0010 8 353bf10ebcSSakari Ailusmodule_date_year 0x0012 8 363bf10ebcSSakari Ailusmodule_date_month 0x0013 8 373bf10ebcSSakari Ailusmodule_date_day 0x0014 8 383bf10ebcSSakari Ailusmodule_date_phase 0x0015 8 393bf10ebcSSakari Ailus- f 0 2 403bf10ebcSSakari Ailus- e ts 0 413bf10ebcSSakari Ailus- e es 1 423bf10ebcSSakari Ailus- e cs 2 433bf10ebcSSakari Ailus- e mp 3 443bf10ebcSSakari Ailussensor_model_id 0x0016 16 453bf10ebcSSakari Ailussensor_revision_number 0x0018 8 463bf10ebcSSakari Ailussensor_firmware_version 0x001a 8 473bf10ebcSSakari Ailusserial_number 0x001c 32 483bf10ebcSSakari Ailussensor_manufacturer_id 0x0020 16 493bf10ebcSSakari Ailussensor_revision_number_16 0x0022 16 503bf10ebcSSakari Ailus 513bf10ebcSSakari Ailus# frame format description registers 523bf10ebcSSakari Ailusframe_format_model_type 0x0040 8 533bf10ebcSSakari Ailus- e 2-byte 1 543bf10ebcSSakari Ailus- e 4-byte 2 553bf10ebcSSakari Ailusframe_format_model_subtype 0x0041 8 563bf10ebcSSakari Ailus- f rows 0 3 573bf10ebcSSakari Ailus- f columns 4 7 583bf10ebcSSakari Ailusframe_format_descriptor(n) 0x0042 16 f 593bf10ebcSSakari Ailus- l n 0 14 2 603bf10ebcSSakari Ailus- f pixels 0 11 613bf10ebcSSakari Ailus- f pcode 12 15 623bf10ebcSSakari Ailus- e embedded 1 633bf10ebcSSakari Ailus- e dummy_pixel 2 643bf10ebcSSakari Ailus- e black_pixel 3 653bf10ebcSSakari Ailus- e dark_pixel 4 663bf10ebcSSakari Ailus- e visible_pixel 5 673bf10ebcSSakari Ailus- e manuf_specific_0 8 683bf10ebcSSakari Ailus- e manuf_specific_1 9 693bf10ebcSSakari Ailus- e manuf_specific_2 10 703bf10ebcSSakari Ailus- e manuf_specific_3 11 713bf10ebcSSakari Ailus- e manuf_specific_4 12 723bf10ebcSSakari Ailus- e manuf_specific_5 13 733bf10ebcSSakari Ailus- e manuf_specific_6 14 743bf10ebcSSakari Ailusframe_format_descriptor_4(n) 0x0060 32 f 753bf10ebcSSakari Ailus- l n 0 7 4 763bf10ebcSSakari Ailus- f pixels 0 15 773bf10ebcSSakari Ailus- f pcode 28 31 783bf10ebcSSakari Ailus- e embedded 1 793bf10ebcSSakari Ailus- e dummy_pixel 2 803bf10ebcSSakari Ailus- e black_pixel 3 813bf10ebcSSakari Ailus- e dark_pixel 4 823bf10ebcSSakari Ailus- e visible_pixel 5 833bf10ebcSSakari Ailus- e manuf_specific_0 8 843bf10ebcSSakari Ailus- e manuf_specific_1 9 853bf10ebcSSakari Ailus- e manuf_specific_2 10 863bf10ebcSSakari Ailus- e manuf_specific_3 11 873bf10ebcSSakari Ailus- e manuf_specific_4 12 883bf10ebcSSakari Ailus- e manuf_specific_5 13 893bf10ebcSSakari Ailus- e manuf_specific_6 14 903bf10ebcSSakari Ailus 913bf10ebcSSakari Ailus# analog gain description registers 923bf10ebcSSakari Ailusanalog_gain_capability 0x0080 16 933bf10ebcSSakari Ailus- e global 0 943bf10ebcSSakari Ailus- e alternate_global 2 953bf10ebcSSakari Ailusanalog_gain_code_min 0x0084 16 963bf10ebcSSakari Ailusanalog_gain_code_max 0x0086 16 973bf10ebcSSakari Ailusanalog_gain_code_step 0x0088 16 983bf10ebcSSakari Ailusanalog_gain_type 0x008a 16 993bf10ebcSSakari Ailusanalog_gain_m0 0x008c 16 1003bf10ebcSSakari Ailusanalog_gain_c0 0x008e 16 1013bf10ebcSSakari Ailusanalog_gain_m1 0x0090 16 1023bf10ebcSSakari Ailusanalog_gain_c1 0x0092 16 1033bf10ebcSSakari Ailusanalog_linear_gain_min 0x0094 16 v1.1 1043bf10ebcSSakari Ailusanalog_linear_gain_max 0x0096 16 v1.1 1053bf10ebcSSakari Ailusanalog_linear_gain_step_size 0x0098 16 v1.1 1063bf10ebcSSakari Ailusanalog_exponential_gain_min 0x009a 16 v1.1 1073bf10ebcSSakari Ailusanalog_exponential_gain_max 0x009c 16 v1.1 1083bf10ebcSSakari Ailusanalog_exponential_gain_step_size 0x009e 16 v1.1 1093bf10ebcSSakari Ailus 1103bf10ebcSSakari Ailus# data format description registers 1113bf10ebcSSakari Ailusdata_format_model_type 0x00c0 8 1123bf10ebcSSakari Ailus- e normal 1 1133bf10ebcSSakari Ailus- e extended 2 1143bf10ebcSSakari Ailusdata_format_model_subtype 0x00c1 8 1153bf10ebcSSakari Ailus- f rows 0 3 1163bf10ebcSSakari Ailus- f columns 4 7 1173bf10ebcSSakari Ailusdata_format_descriptor(n) 0x00c2 16 f 1183bf10ebcSSakari Ailus- l n 0 15 2 1193bf10ebcSSakari Ailus- f compressed 0 7 1203bf10ebcSSakari Ailus- f uncompressed 8 15 1213bf10ebcSSakari Ailus 1223bf10ebcSSakari Ailus# general set-up registers 1233bf10ebcSSakari Ailusmode_select 0x0100 8 1243bf10ebcSSakari Ailus- e software_standby 0 1253bf10ebcSSakari Ailus- e streaming 1 1263bf10ebcSSakari Ailusimage_orientation 0x0101 8 1273bf10ebcSSakari Ailus- b horizontal_mirror 0 1283bf10ebcSSakari Ailus- b vertical_flip 1 1293bf10ebcSSakari Ailussoftware_reset 0x0103 8 1303bf10ebcSSakari Ailus- e off 0 1313bf10ebcSSakari Ailus- e on 1 1323bf10ebcSSakari Ailusgrouped_parameter_hold 0x0104 8 1333bf10ebcSSakari Ailusmask_corrupted_frames 0x0105 8 1343bf10ebcSSakari Ailus- e allow 0 1353bf10ebcSSakari Ailus- e mask 1 1363bf10ebcSSakari Ailusfast_standby_ctrl 0x0106 8 1373bf10ebcSSakari Ailus- e complete_frames 0 1383bf10ebcSSakari Ailus- e frame_truncation 1 1393bf10ebcSSakari AilusCCI_address_ctrl 0x0107 8 1403bf10ebcSSakari Ailus2nd_CCI_if_ctrl 0x0108 8 1413bf10ebcSSakari Ailus- b enable 0 1423bf10ebcSSakari Ailus- b ack 1 1433bf10ebcSSakari Ailus2nd_CCI_address_ctrl 0x0109 8 1443bf10ebcSSakari AilusCSI_channel_identifier 0x0110 8 1453bf10ebcSSakari AilusCSI_signaling_mode 0x0111 8 1463bf10ebcSSakari Ailus- e csi_2_dphy 2 1473bf10ebcSSakari Ailus- e csi_2_cphy 3 1483bf10ebcSSakari AilusCSI_data_format 0x0112 16 1493bf10ebcSSakari AilusCSI_lane_mode 0x0114 8 1503bf10ebcSSakari AilusDPCM_Frame_DT 0x011d 8 1513bf10ebcSSakari AilusBottom_embedded_data_DT 0x011e 8 1523bf10ebcSSakari AilusBottom_embedded_data_VC 0x011f 8 1533bf10ebcSSakari Ailus 1543bf10ebcSSakari Ailusgain_mode 0x0120 8 1553bf10ebcSSakari Ailus- e global 0 1563bf10ebcSSakari Ailus- e alternate 1 1573bf10ebcSSakari AilusADC_bit_depth 0x0121 8 1583bf10ebcSSakari Ailusemb_data_ctrl 0x0122 v1.1 1593bf10ebcSSakari Ailus- b raw8_packing_for_raw16 0 1603bf10ebcSSakari Ailus- b raw10_packing_for_raw20 1 1613bf10ebcSSakari Ailus- b raw12_packing_for_raw24 2 1623bf10ebcSSakari Ailus 1633bf10ebcSSakari AilusGPIO_TRIG_mode 0x0130 8 1643bf10ebcSSakari Ailusextclk_frequency_mhz 0x0136 16 ireal 1653bf10ebcSSakari Ailustemp_sensor_ctrl 0x0138 8 1663bf10ebcSSakari Ailus- b enable 0 1673bf10ebcSSakari Ailustemp_sensor_mode 0x0139 8 1683bf10ebcSSakari Ailustemp_sensor_output 0x013a 8 1693bf10ebcSSakari Ailus 1703bf10ebcSSakari Ailus# integration time registers 1713bf10ebcSSakari Ailusfine_integration_time 0x0200 16 1723bf10ebcSSakari Ailuscoarse_integration_time 0x0202 16 1733bf10ebcSSakari Ailus 1743bf10ebcSSakari Ailus# analog gain registers 1753bf10ebcSSakari Ailusanalog_gain_code_global 0x0204 16 1763bf10ebcSSakari Ailusanalog_linear_gain_global 0x0206 16 v1.1 1773bf10ebcSSakari Ailusanalog_exponential_gain_global 0x0208 16 v1.1 1783bf10ebcSSakari Ailus 1793bf10ebcSSakari Ailus# digital gain registers 1803bf10ebcSSakari Ailusdigital_gain_global 0x020e 16 1813bf10ebcSSakari Ailus 1823bf10ebcSSakari Ailus# hdr control registers 1833bf10ebcSSakari AilusShort_analog_gain_global 0x0216 16 1843bf10ebcSSakari AilusShort_digital_gain_global 0x0218 16 1853bf10ebcSSakari Ailus 1863bf10ebcSSakari AilusHDR_mode 0x0220 8 1873bf10ebcSSakari Ailus- b enabled 0 1883bf10ebcSSakari Ailus- b separate_analog_gain 1 1893bf10ebcSSakari Ailus- b upscaling 2 1903bf10ebcSSakari Ailus- b reset_sync 3 1913bf10ebcSSakari Ailus- b timing_mode 4 1923bf10ebcSSakari Ailus- b exposure_ctrl_direct 5 1933bf10ebcSSakari Ailus- b separate_digital_gain 6 1943bf10ebcSSakari AilusHDR_resolution_reduction 0x0221 8 1953bf10ebcSSakari Ailus- f row 0 3 1963bf10ebcSSakari Ailus- f column 4 7 1973bf10ebcSSakari AilusExposure_ratio 0x0222 8 1983bf10ebcSSakari AilusHDR_internal_bit_depth 0x0223 8 1993bf10ebcSSakari AilusDirect_short_integration_time 0x0224 16 2003bf10ebcSSakari AilusShort_analog_linear_gain_global 0x0226 16 v1.1 2013bf10ebcSSakari AilusShort_analog_exponential_gain_global 0x0228 16 v1.1 2023bf10ebcSSakari Ailus 2033bf10ebcSSakari Ailus# clock set-up registers 2043bf10ebcSSakari Ailusvt_pix_clk_div 0x0300 16 2053bf10ebcSSakari Ailusvt_sys_clk_div 0x0302 16 2063bf10ebcSSakari Ailuspre_pll_clk_div 0x0304 16 2073bf10ebcSSakari Ailus#vt_pre_pll_clk_div 0x0304 16 2083bf10ebcSSakari Ailuspll_multiplier 0x0306 16 2093bf10ebcSSakari Ailus#vt_pll_multiplier 0x0306 16 2103bf10ebcSSakari Ailusop_pix_clk_div 0x0308 16 2113bf10ebcSSakari Ailusop_sys_clk_div 0x030a 16 2123bf10ebcSSakari Ailusop_pre_pll_clk_div 0x030c 16 2133bf10ebcSSakari Ailusop_pll_multiplier 0x031e 16 2143bf10ebcSSakari Ailuspll_mode 0x0310 8 2153bf10ebcSSakari Ailus- f 0 0 2163bf10ebcSSakari Ailus- e single 0 2173bf10ebcSSakari Ailus- e dual 1 2183bf10ebcSSakari Ailusop_pix_clk_div_rev 0x0312 16 v1.1 2193bf10ebcSSakari Ailusop_sys_clk_div_rev 0x0314 16 v1.1 2203bf10ebcSSakari Ailus 2213bf10ebcSSakari Ailus# frame timing registers 2223bf10ebcSSakari Ailusframe_length_lines 0x0340 16 2233bf10ebcSSakari Ailusline_length_pck 0x0342 16 2243bf10ebcSSakari Ailus 2253bf10ebcSSakari Ailus# image size registers 2263bf10ebcSSakari Ailusx_addr_start 0x0344 16 2273bf10ebcSSakari Ailusy_addr_start 0x0346 16 2283bf10ebcSSakari Ailusx_addr_end 0x0348 16 2293bf10ebcSSakari Ailusy_addr_end 0x034a 16 2303bf10ebcSSakari Ailusx_output_size 0x034c 16 2313bf10ebcSSakari Ailusy_output_size 0x034e 16 2323bf10ebcSSakari Ailus 2333bf10ebcSSakari Ailus# timing mode registers 2343bf10ebcSSakari AilusFrame_length_ctrl 0x0350 8 2353bf10ebcSSakari Ailus- b automatic 0 2363bf10ebcSSakari AilusTiming_mode_ctrl 0x0352 8 2373bf10ebcSSakari Ailus- b manual_readout 0 2383bf10ebcSSakari Ailus- b delayed_exposure 1 2393bf10ebcSSakari AilusStart_readout_rs 0x0353 8 2403bf10ebcSSakari Ailus- b manual_readout_start 0 2413bf10ebcSSakari AilusFrame_margin 0x0354 16 2423bf10ebcSSakari Ailus 2433bf10ebcSSakari Ailus# sub-sampling registers 2443bf10ebcSSakari Ailusx_even_inc 0x0380 16 2453bf10ebcSSakari Ailusx_odd_inc 0x0382 16 2463bf10ebcSSakari Ailusy_even_inc 0x0384 16 2473bf10ebcSSakari Ailusy_odd_inc 0x0386 16 2483bf10ebcSSakari Ailus 2493bf10ebcSSakari Ailus# monochrome readout registers 2503bf10ebcSSakari Ailusmonochrome_en 0x0390 v1.1 2513bf10ebcSSakari Ailus- e enabled 0 2523bf10ebcSSakari Ailus 2533bf10ebcSSakari Ailus# image scaling registers 2543bf10ebcSSakari AilusScaling_mode 0x0400 16 2553bf10ebcSSakari Ailus- e no_scaling 0 2563bf10ebcSSakari Ailus- e horizontal 1 2573bf10ebcSSakari Ailusscale_m 0x0404 16 2583bf10ebcSSakari Ailusscale_n 0x0406 16 2593bf10ebcSSakari Ailusdigital_crop_x_offset 0x0408 16 2603bf10ebcSSakari Ailusdigital_crop_y_offset 0x040a 16 2613bf10ebcSSakari Ailusdigital_crop_image_width 0x040c 16 2623bf10ebcSSakari Ailusdigital_crop_image_height 0x040e 16 2633bf10ebcSSakari Ailus 2643bf10ebcSSakari Ailus# image compression registers 2653bf10ebcSSakari Ailuscompression_mode 0x0500 16 2663bf10ebcSSakari Ailus- e none 0 2673bf10ebcSSakari Ailus- e dpcm_pcm_simple 1 2683bf10ebcSSakari Ailus 2693bf10ebcSSakari Ailus# test pattern registers 2703bf10ebcSSakari Ailustest_pattern_mode 0x0600 16 2713bf10ebcSSakari Ailus- e none 0 2723bf10ebcSSakari Ailus- e solid_color 1 2733bf10ebcSSakari Ailus- e color_bars 2 2743bf10ebcSSakari Ailus- e fade_to_grey 3 2753bf10ebcSSakari Ailus- e pn9 4 2763bf10ebcSSakari Ailus- e color_tile 5 2773bf10ebcSSakari Ailustest_data_red 0x0602 16 2783bf10ebcSSakari Ailustest_data_greenR 0x0604 16 2793bf10ebcSSakari Ailustest_data_blue 0x0606 16 2803bf10ebcSSakari Ailustest_data_greenB 0x0608 16 2813bf10ebcSSakari Ailusvalue_step_size_smooth 0x060a 8 2823bf10ebcSSakari Ailusvalue_step_size_quantised 0x060b 8 2833bf10ebcSSakari Ailus 2843bf10ebcSSakari Ailus# phy configuration registers 2853bf10ebcSSakari Ailustclk_post 0x0800 8 2863bf10ebcSSakari Ailusths_prepare 0x0801 8 2873bf10ebcSSakari Ailusths_zero_min 0x0802 8 2883bf10ebcSSakari Ailusths_trail 0x0803 8 2893bf10ebcSSakari Ailustclk_trail_min 0x0804 8 2903bf10ebcSSakari Ailustclk_prepare 0x0805 8 2913bf10ebcSSakari Ailustclk_zero 0x0806 8 2923bf10ebcSSakari Ailustlpx 0x0807 8 2933bf10ebcSSakari Ailusphy_ctrl 0x0808 8 2943bf10ebcSSakari Ailus- e auto 0 2953bf10ebcSSakari Ailus- e UI 1 2963bf10ebcSSakari Ailus- e manual 2 2973bf10ebcSSakari Ailustclk_post_ex 0x080a 16 2983bf10ebcSSakari Ailusths_prepare_ex 0x080c 16 2993bf10ebcSSakari Ailusths_zero_min_ex 0x080e 16 3003bf10ebcSSakari Ailusths_trail_ex 0x0810 16 3013bf10ebcSSakari Ailustclk_trail_min_ex 0x0812 16 3023bf10ebcSSakari Ailustclk_prepare_ex 0x0814 16 3033bf10ebcSSakari Ailustclk_zero_ex 0x0816 16 3043bf10ebcSSakari Ailustlpx_ex 0x0818 16 3053bf10ebcSSakari Ailus 3063bf10ebcSSakari Ailus# link rate register 3073bf10ebcSSakari Ailusrequested_link_rate 0x0820 32 u16.16 3083bf10ebcSSakari Ailus 3093bf10ebcSSakari Ailus# equalization control registers 3103bf10ebcSSakari AilusDPHY_equalization_mode 0x0824 8 v1.1 3113bf10ebcSSakari Ailus- b eq2 0 3123bf10ebcSSakari AilusPHY_equalization_ctrl 0x0825 8 v1.1 3133bf10ebcSSakari Ailus- b enable 0 3143bf10ebcSSakari Ailus 3153bf10ebcSSakari Ailus# d-phy preamble control registers 3163bf10ebcSSakari AilusDPHY_preamble_ctrl 0x0826 8 v1.1 3173bf10ebcSSakari Ailus- b enable 0 3183bf10ebcSSakari AilusDPHY_preamble_length 0x0826 8 v1.1 3193bf10ebcSSakari Ailus 3203bf10ebcSSakari Ailus# d-phy spread spectrum control registers 3213bf10ebcSSakari AilusPHY_SSC_ctrl 0x0828 8 v1.1 3223bf10ebcSSakari Ailus- b enable 0 3233bf10ebcSSakari Ailus 3243bf10ebcSSakari Ailus# manual lp control register 3253bf10ebcSSakari Ailusmanual_LP_ctrl 0x0829 8 v1.1 3263bf10ebcSSakari Ailus- b enable 0 3273bf10ebcSSakari Ailus 3283bf10ebcSSakari Ailus# additional phy configuration registers 3293bf10ebcSSakari Ailustwakeup 0x082a v1.1 3303bf10ebcSSakari Ailustinit 0x082b v1.1 3313bf10ebcSSakari Ailusths_exit 0x082c v1.1 3323bf10ebcSSakari Ailusths_exit_ex 0x082e 16 v1.1 3333bf10ebcSSakari Ailus 3343bf10ebcSSakari Ailus# phy calibration configuration registers 3353bf10ebcSSakari AilusPHY_periodic_calibration_ctrl 0x0830 8 3363bf10ebcSSakari Ailus- b frame_blanking 0 3373bf10ebcSSakari AilusPHY_periodic_calibration_interval 0x0831 8 3383bf10ebcSSakari AilusPHY_init_calibration_ctrl 0x0832 8 3393bf10ebcSSakari Ailus- b stream_start 0 3403bf10ebcSSakari AilusDPHY_calibration_mode 0x0833 8 v1.1 3413bf10ebcSSakari Ailus- b also_alternate 0 3423bf10ebcSSakari AilusCPHY_calibration_mode 0x0834 8 v1.1 3433bf10ebcSSakari Ailus- e format_1 0 3443bf10ebcSSakari Ailus- e format_2 1 3453bf10ebcSSakari Ailus- e format_3 2 3463bf10ebcSSakari Ailust3_calpreamble_length 0x0835 8 v1.1 3473bf10ebcSSakari Ailust3_calpreamble_length_per 0x0836 8 v1.1 3483bf10ebcSSakari Ailust3_calaltseq_length 0x0837 8 v1.1 3493bf10ebcSSakari Ailust3_calaltseq_length_per 0x0838 8 v1.1 3503bf10ebcSSakari AilusFM2_init_seed 0x083a 16 v1.1 3513bf10ebcSSakari Ailust3_caludefseq_length 0x083c 16 v1.1 3523bf10ebcSSakari Ailust3_caludefseq_length_per 0x083e 16 v1.1 3533bf10ebcSSakari Ailus 3543bf10ebcSSakari Ailus# c-phy manual control registers 3553bf10ebcSSakari AilusTGR_Preamble_Length 0x0841 8 3563bf10ebcSSakari Ailus- b preamable_prog_seq 7 3573bf10ebcSSakari Ailus- f begin_preamble_length 0 5 3583bf10ebcSSakari AilusTGR_Post_Length 0x0842 8 3593bf10ebcSSakari Ailus- f post_length 0 4 3603bf10ebcSSakari AilusTGR_Preamble_Prog_Sequence(n2) 0x0843 3613bf10ebcSSakari Ailus- l n2 0 6 1 3623bf10ebcSSakari Ailus- f symbol_n_1 3 5 3633bf10ebcSSakari Ailus- f symbol_n 0 2 3643bf10ebcSSakari Ailust3_prepare 0x084e 16 3653bf10ebcSSakari Ailust3_lpx 0x0850 16 3663bf10ebcSSakari Ailus 3673bf10ebcSSakari Ailus# alps control register 3683bf10ebcSSakari AilusALPS_ctrl 0x085a 8 3693bf10ebcSSakari Ailus- b lvlp_dphy 0 3703bf10ebcSSakari Ailus- b lvlp_cphy 1 3713bf10ebcSSakari Ailus- b alp_cphy 2 3723bf10ebcSSakari Ailus 3733bf10ebcSSakari Ailus# lrte control registers 3743bf10ebcSSakari AilusTX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16 3753bf10ebcSSakari AilusTX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16 3763bf10ebcSSakari AilusTX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16 3773bf10ebcSSakari AilusTX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16 3783bf10ebcSSakari AilusTX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1 3793bf10ebcSSakari AilusTX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1 3803bf10ebcSSakari Ailus 3813bf10ebcSSakari Ailus# scrambling control registers 3823bf10ebcSSakari AilusScrambling_ctrl 0x0870 3833bf10ebcSSakari Ailus- b enabled 0 3843bf10ebcSSakari Ailus- f 2 3 3853bf10ebcSSakari Ailus- e 1_seed_cphy 0 3863bf10ebcSSakari Ailus- e 4_seed_cphy 3 3873bf10ebcSSakari Ailuslane_seed_value(seed, lane) 0x0872 16 3883bf10ebcSSakari Ailus- l seed 0 3 0x10 3893bf10ebcSSakari Ailus- l lane 0 7 0x2 3903bf10ebcSSakari Ailus 3913bf10ebcSSakari Ailus# usl control registers 3923bf10ebcSSakari AilusTX_USL_REV_ENTRY 0x08c0 16 v1.1 3933bf10ebcSSakari AilusTX_USL_REV_Clock_Counter 0x08c2 16 v1.1 3943bf10ebcSSakari AilusTX_USL_REV_LP_Counter 0x08c4 16 v1.1 3953bf10ebcSSakari AilusTX_USL_REV_Frame_Counter 0x08c6 16 v1.1 3963bf10ebcSSakari AilusTX_USL_REV_Chronological_Timer 0x08c8 16 v1.1 3973bf10ebcSSakari AilusTX_USL_FWD_ENTRY 0x08ca 16 v1.1 3983bf10ebcSSakari AilusTX_USL_GPIO 0x08cc 16 v1.1 3993bf10ebcSSakari AilusTX_USL_Operation 0x08ce 16 v1.1 4003bf10ebcSSakari Ailus- b reset 0 4013bf10ebcSSakari AilusTX_USL_ALP_ctrl 0x08d0 16 v1.1 4023bf10ebcSSakari Ailus- b clock_pause 0 4033bf10ebcSSakari AilusTX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 4043bf10ebcSSakari AilusTX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 4053bf10ebcSSakari AilusUSL_Clock_Mode_d_ctrl 0x08d2 v1.1 4063bf10ebcSSakari Ailus- b cont_clock_standby 0 4073bf10ebcSSakari Ailus- b cont_clock_vblank 1 4083bf10ebcSSakari Ailus- b cont_clock_hblank 2 4093bf10ebcSSakari Ailus 4103bf10ebcSSakari Ailus# binning configuration registers 4113bf10ebcSSakari Ailusbinning_mode 0x0900 8 4123bf10ebcSSakari Ailusbinning_type 0x0901 8 4133bf10ebcSSakari Ailusbinning_weighting 0x0902 8 4143bf10ebcSSakari Ailus 4153bf10ebcSSakari Ailus# data transfer interface registers 4163bf10ebcSSakari Ailusdata_transfer_if_1_ctrl 0x0a00 8 4173bf10ebcSSakari Ailus- b enable 0 4183bf10ebcSSakari Ailus- b write 1 4193bf10ebcSSakari Ailus- b clear_error 2 4203bf10ebcSSakari Ailusdata_transfer_if_1_status 0x0a01 8 4213bf10ebcSSakari Ailus- b read_if_ready 0 4223bf10ebcSSakari Ailus- b write_if_ready 1 4233bf10ebcSSakari Ailus- b data_corrupted 2 4243bf10ebcSSakari Ailus- b improper_if_usage 3 4253bf10ebcSSakari Ailusdata_transfer_if_1_page_select 0x0a02 8 4263bf10ebcSSakari Ailusdata_transfer_if_1_data(p) 0x0a04 8 f 4273bf10ebcSSakari Ailus- l p 0 63 1 4283bf10ebcSSakari Ailus 4293bf10ebcSSakari Ailus# image processing and sensor correction configuration registers 4303bf10ebcSSakari Ailusshading_correction_en 0x0b00 8 4313bf10ebcSSakari Ailus- b enable 0 4323bf10ebcSSakari Ailusluminance_correction_level 0x0b01 8 4333bf10ebcSSakari Ailusgreen_imbalance_filter_en 0x0b02 8 4343bf10ebcSSakari Ailus- b enable 0 4353bf10ebcSSakari Ailusmapped_defect_correct_en 0x0b05 8 4363bf10ebcSSakari Ailus- b enable 0 4373bf10ebcSSakari Ailussingle_defect_correct_en 0x0b06 8 4383bf10ebcSSakari Ailus- b enable 0 4393bf10ebcSSakari Ailusdynamic_couplet_correct_en 0x0b08 8 4403bf10ebcSSakari Ailus- b enable 0 4413bf10ebcSSakari Ailuscombined_defect_correct_en 0x0b0a 8 4423bf10ebcSSakari Ailus- b enable 0 4433bf10ebcSSakari Ailusmodule_specific_correction_en 0x0b0c 8 4443bf10ebcSSakari Ailus- b enable 0 4453bf10ebcSSakari Ailusdynamic_triplet_defect_correct_en 0x0b13 8 4463bf10ebcSSakari Ailus- b enable 0 4473bf10ebcSSakari AilusNF_ctrl 0x0b15 8 4483bf10ebcSSakari Ailus- b luma 0 4493bf10ebcSSakari Ailus- b chroma 1 4503bf10ebcSSakari Ailus- b combined 2 4513bf10ebcSSakari Ailus 4523bf10ebcSSakari Ailus# optical black pixel readout registers 4533bf10ebcSSakari AilusOB_readout_control 0x0b30 8 4543bf10ebcSSakari Ailus- b enable 0 4553bf10ebcSSakari Ailus- b interleaving 1 4563bf10ebcSSakari AilusOB_virtual_channel 0x0b31 8 4573bf10ebcSSakari AilusOB_DT 0x0b32 8 4583bf10ebcSSakari AilusOB_data_format 0x0b33 8 4593bf10ebcSSakari Ailus 4603bf10ebcSSakari Ailus# color temperature feedback registers 4613bf10ebcSSakari Ailuscolor_temperature 0x0b8c 16 4623bf10ebcSSakari Ailusabsolute_gain_greenr 0x0b8e 16 4633bf10ebcSSakari Ailusabsolute_gain_red 0x0b90 16 4643bf10ebcSSakari Ailusabsolute_gain_blue 0x0b92 16 4653bf10ebcSSakari Ailusabsolute_gain_greenb 0x0b94 16 4663bf10ebcSSakari Ailus 4673bf10ebcSSakari Ailus# cfa conversion registers 4683bf10ebcSSakari AilusCFA_conversion_ctrl 0x0ba0 v1.1 4693bf10ebcSSakari Ailus- b bayer_conversion_enable 0 4703bf10ebcSSakari Ailus 4713bf10ebcSSakari Ailus# flash strobe and sa strobe control registers 4723bf10ebcSSakari Ailusflash_strobe_adjustment 0x0c12 8 4733bf10ebcSSakari Ailusflash_strobe_start_point 0x0c14 16 4743bf10ebcSSakari Ailustflash_strobe_delay_rs_ctrl 0x0c16 16 4753bf10ebcSSakari Ailustflash_strobe_width_high_rs_ctrl 0x0c18 16 4763bf10ebcSSakari Ailusflash_mode_rs 0x0c1a 8 4773bf10ebcSSakari Ailus- b continuous 0 4783bf10ebcSSakari Ailus- b truncate 1 4793bf10ebcSSakari Ailus- b async 3 4803bf10ebcSSakari Ailusflash_trigger_rs 0x0c1b 8 4813bf10ebcSSakari Ailusflash_status 0x0c1c 8 4823bf10ebcSSakari Ailus- b retimed 0 4833bf10ebcSSakari Ailussa_strobe_mode 0x0c1d 8 4843bf10ebcSSakari Ailus- b continuous 0 4853bf10ebcSSakari Ailus- b truncate 1 4863bf10ebcSSakari Ailus- b async 3 4873bf10ebcSSakari Ailus- b adjust_edge 4 4883bf10ebcSSakari Ailussa_strobe_start_point 0x0c1e 16 4893bf10ebcSSakari Ailustsa_strobe_delay_ctrl 0x0c20 16 4903bf10ebcSSakari Ailustsa_strobe_width_ctrl 0x0c22 16 4913bf10ebcSSakari Ailussa_strobe_trigger 0x0c24 8 4923bf10ebcSSakari Ailussa_strobe_status 0x0c25 8 4933bf10ebcSSakari Ailus- b retimed 0 4943bf10ebcSSakari AilustSA_strobe_re_delay_ctrl 0x0c30 16 4953bf10ebcSSakari AilustSA_strobe_fe_delay_ctrl 0x0c32 16 4963bf10ebcSSakari Ailus 4973bf10ebcSSakari Ailus# pdaf control registers 4983bf10ebcSSakari AilusPDAF_ctrl 0x0d00 16 4993bf10ebcSSakari Ailus- b enable 0 5003bf10ebcSSakari Ailus- b processed 1 5013bf10ebcSSakari Ailus- b interleaved 2 5023bf10ebcSSakari Ailus- b visible_pdaf_correction 3 5033bf10ebcSSakari AilusPDAF_VC 0x0d02 8 5043bf10ebcSSakari AilusPDAF_DT 0x0d03 8 5053bf10ebcSSakari Ailuspd_x_addr_start 0x0d04 16 5063bf10ebcSSakari Ailuspd_y_addr_start 0x0d06 16 5073bf10ebcSSakari Ailuspd_x_addr_end 0x0d08 16 5083bf10ebcSSakari Ailuspd_y_addr_end 0x0d0a 16 5093bf10ebcSSakari Ailus 5103bf10ebcSSakari Ailus# bracketing interface configuration registers 5113bf10ebcSSakari Ailusbracketing_LUT_ctrl 0x0e00 8 5123bf10ebcSSakari Ailusbracketing_LUT_mode 0x0e01 8 5133bf10ebcSSakari Ailus- b continue_streaming 0 5143bf10ebcSSakari Ailus- b loop_mode 1 5153bf10ebcSSakari Ailusbracketing_LUT_entry_ctrl 0x0e02 8 5163bf10ebcSSakari Ailusbracketing_LUT_frame(n) 0x0e10 v1.1 f 5173bf10ebcSSakari Ailus- l n 0 0xef 1 5183bf10ebcSSakari Ailus 5193bf10ebcSSakari Ailus# integration time and gain parameter limit registers 5203bf10ebcSSakari Ailusintegration_time_capability 0x1000 16 5213bf10ebcSSakari Ailus- b fine 0 5223bf10ebcSSakari Ailuscoarse_integration_time_min 0x1004 16 5233bf10ebcSSakari Ailuscoarse_integration_time_max_margin 0x1006 16 5243bf10ebcSSakari Ailusfine_integration_time_min 0x1008 16 5253bf10ebcSSakari Ailusfine_integration_time_max_margin 0x100a 16 5263bf10ebcSSakari Ailus 5273bf10ebcSSakari Ailus# digital gain parameter limit registers 5283bf10ebcSSakari Ailusdigital_gain_capability 0x1081 5293bf10ebcSSakari Ailus- e none 0 5303bf10ebcSSakari Ailus- e global 2 5313bf10ebcSSakari Ailusdigital_gain_min 0x1084 16 5323bf10ebcSSakari Ailusdigital_gain_max 0x1086 16 5333bf10ebcSSakari Ailusdigital_gain_step_size 0x1088 16 5343bf10ebcSSakari Ailus 5353bf10ebcSSakari Ailus# data pedestal capability registers 5363bf10ebcSSakari AilusPedestal_capability 0x10e0 8 v1.1 5373bf10ebcSSakari Ailus 5383bf10ebcSSakari Ailus# adc capability registers 5393bf10ebcSSakari AilusADC_capability 0x10f0 8 5403bf10ebcSSakari Ailus- b bit_depth_ctrl 0 5413bf10ebcSSakari AilusADC_bit_depth_capability 0x10f4 32 v1.1 5423bf10ebcSSakari Ailus 5433bf10ebcSSakari Ailus# video timing parameter limit registers 5443bf10ebcSSakari Ailusmin_ext_clk_freq_mhz 0x1100 32 float_ireal 5453bf10ebcSSakari Ailusmax_ext_clk_freq_mhz 0x1104 32 float_ireal 5463bf10ebcSSakari Ailusmin_pre_pll_clk_div 0x1108 16 5473bf10ebcSSakari Ailus# min_vt_pre_pll_clk_div 0x1108 16 5483bf10ebcSSakari Ailusmax_pre_pll_clk_div 0x110a 16 5493bf10ebcSSakari Ailus# max_vt_pre_pll_clk_div 0x110a 16 5503bf10ebcSSakari Ailusmin_pll_ip_clk_freq_mhz 0x110c 32 float_ireal 5513bf10ebcSSakari Ailus# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal 5523bf10ebcSSakari Ailusmax_pll_ip_clk_freq_mhz 0x1110 32 float_ireal 5533bf10ebcSSakari Ailus# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal 5543bf10ebcSSakari Ailusmin_pll_multiplier 0x1114 16 5553bf10ebcSSakari Ailus# min_vt_pll_multiplier 0x1114 16 5563bf10ebcSSakari Ailusmax_pll_multiplier 0x1116 16 5573bf10ebcSSakari Ailus# max_vt_pll_multiplier 0x1116 16 5583bf10ebcSSakari Ailusmin_pll_op_clk_freq_mhz 0x1118 32 float_ireal 5593bf10ebcSSakari Ailusmax_pll_op_clk_freq_mhz 0x111c 32 float_ireal 5603bf10ebcSSakari Ailus 5613bf10ebcSSakari Ailus# video timing set-up capability registers 5623bf10ebcSSakari Ailusmin_vt_sys_clk_div 0x1120 16 5633bf10ebcSSakari Ailusmax_vt_sys_clk_div 0x1122 16 5643bf10ebcSSakari Ailusmin_vt_sys_clk_freq_mhz 0x1124 32 float_ireal 5653bf10ebcSSakari Ailusmax_vt_sys_clk_freq_mhz 0x1128 32 float_ireal 5663bf10ebcSSakari Ailusmin_vt_pix_clk_freq_mhz 0x112c 32 float_ireal 5673bf10ebcSSakari Ailusmax_vt_pix_clk_freq_mhz 0x1130 32 float_ireal 5683bf10ebcSSakari Ailusmin_vt_pix_clk_div 0x1134 16 5693bf10ebcSSakari Ailusmax_vt_pix_clk_div 0x1136 16 5703bf10ebcSSakari Ailusclock_calculation 0x1138 5713bf10ebcSSakari Ailus- b lane_speed 0 5723bf10ebcSSakari Ailus- b link_decoupled 1 5733bf10ebcSSakari Ailus- b dual_pll_op_sys_ddr 2 5743bf10ebcSSakari Ailus- b dual_pll_op_pix_ddr 3 5753bf10ebcSSakari Ailusnum_of_vt_lanes 0x1139 5763bf10ebcSSakari Ailusnum_of_op_lanes 0x113a 5773bf10ebcSSakari Ailusop_bits_per_lane 0x113b 8 v1.1 5783bf10ebcSSakari Ailus 5793bf10ebcSSakari Ailus# frame timing parameter limits 5803bf10ebcSSakari Ailusmin_frame_length_lines 0x1140 16 5813bf10ebcSSakari Ailusmax_frame_length_lines 0x1142 16 5823bf10ebcSSakari Ailusmin_line_length_pck 0x1144 16 5833bf10ebcSSakari Ailusmax_line_length_pck 0x1146 16 5843bf10ebcSSakari Ailusmin_line_blanking_pck 0x1148 16 5853bf10ebcSSakari Ailusmin_frame_blanking_lines 0x114a 16 5863bf10ebcSSakari Ailusmin_line_length_pck_step_size 0x114c 5873bf10ebcSSakari Ailustiming_mode_capability 0x114d 5883bf10ebcSSakari Ailus- b auto_frame_length 0 5893bf10ebcSSakari Ailus- b rolling_shutter_manual_readout 2 5903bf10ebcSSakari Ailus- b delayed_exposure_start 3 5913bf10ebcSSakari Ailus- b manual_exposure_embedded_data 4 5923bf10ebcSSakari Ailusframe_margin_max_value 0x114e 16 5933bf10ebcSSakari Ailusframe_margin_min_value 0x1150 5943bf10ebcSSakari Ailusgain_delay_type 0x1151 5953bf10ebcSSakari Ailus- e fixed 0 5963bf10ebcSSakari Ailus- e variable 1 5973bf10ebcSSakari Ailus 5983bf10ebcSSakari Ailus# output clock set-up capability registers 5993bf10ebcSSakari Ailusmin_op_sys_clk_div 0x1160 16 6003bf10ebcSSakari Ailusmax_op_sys_clk_div 0x1162 16 6013bf10ebcSSakari Ailusmin_op_sys_clk_freq_mhz 0x1164 32 float_ireal 6023bf10ebcSSakari Ailusmax_op_sys_clk_freq_mhz 0x1168 32 float_ireal 6033bf10ebcSSakari Ailusmin_op_pix_clk_div 0x116c 16 6043bf10ebcSSakari Ailusmax_op_pix_clk_div 0x116e 16 6053bf10ebcSSakari Ailusmin_op_pix_clk_freq_mhz 0x1170 32 float_ireal 6063bf10ebcSSakari Ailusmax_op_pix_clk_freq_mhz 0x1174 32 float_ireal 6073bf10ebcSSakari Ailus 6083bf10ebcSSakari Ailus# image size parameter limit registers 6093bf10ebcSSakari Ailusx_addr_min 0x1180 16 6103bf10ebcSSakari Ailusy_addr_min 0x1182 16 6113bf10ebcSSakari Ailusx_addr_max 0x1184 16 6123bf10ebcSSakari Ailusy_addr_max 0x1186 16 6133bf10ebcSSakari Ailusmin_x_output_size 0x1188 16 6143bf10ebcSSakari Ailusmin_y_output_size 0x118a 16 6153bf10ebcSSakari Ailusmax_x_output_size 0x118c 16 6163bf10ebcSSakari Ailusmax_y_output_size 0x118e 16 6173bf10ebcSSakari Ailus 6183bf10ebcSSakari Ailusx_addr_start_div_constant 0x1190 v1.1 6193bf10ebcSSakari Ailusy_addr_start_div_constant 0x1191 v1.1 6203bf10ebcSSakari Ailusx_addr_end_div_constant 0x1192 v1.1 6213bf10ebcSSakari Ailusy_addr_end_div_constant 0x1193 v1.1 6223bf10ebcSSakari Ailusx_size_div 0x1194 v1.1 6233bf10ebcSSakari Ailusy_size_div 0x1195 v1.1 6243bf10ebcSSakari Ailusx_output_div 0x1196 v1.1 6253bf10ebcSSakari Ailusy_output_div 0x1197 v1.1 6263bf10ebcSSakari Ailusnon_flexible_resolution_support 0x1198 v1.1 6273bf10ebcSSakari Ailus- b new_pix_addr 0 6283bf10ebcSSakari Ailus- b new_output_res 1 6293bf10ebcSSakari Ailus- b output_crop_no_pad 2 6303bf10ebcSSakari Ailus- b output_size_lane_dep 3 6313bf10ebcSSakari Ailus 6323bf10ebcSSakari Ailusmin_op_pre_pll_clk_div 0x11a0 16 6333bf10ebcSSakari Ailusmax_op_pre_pll_clk_div 0x11a2 16 6343bf10ebcSSakari Ailusmin_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal 6353bf10ebcSSakari Ailusmax_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal 6363bf10ebcSSakari Ailusmin_op_pll_multiplier 0x11ac 16 6373bf10ebcSSakari Ailusmax_op_pll_multiplier 0x11ae 16 6383bf10ebcSSakari Ailusmin_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal 6393bf10ebcSSakari Ailusmax_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal 6403bf10ebcSSakari Ailusclock_tree_pll_capability 0x11b8 8 6413bf10ebcSSakari Ailus- b dual_pll 0 6423bf10ebcSSakari Ailus- b single_pll 1 6433bf10ebcSSakari Ailus- b ext_divider 2 6443bf10ebcSSakari Ailus- b flexible_op_pix_clk_div 3 6453bf10ebcSSakari Ailusclock_capa_type_capability 0x11b9 v1.1 6463bf10ebcSSakari Ailus- b ireal 0 6473bf10ebcSSakari Ailus 6483bf10ebcSSakari Ailus# sub-sampling parameters limit registers 6493bf10ebcSSakari Ailusmin_even_inc 0x11c0 16 6503bf10ebcSSakari Ailusmin_odd_inc 0x11c2 16 6513bf10ebcSSakari Ailusmax_even_inc 0x11c4 16 6523bf10ebcSSakari Ailusmax_odd_inc 0x11c6 16 6533bf10ebcSSakari Ailusaux_subsamp_capability 0x11c8 v1.1 6543bf10ebcSSakari Ailus- b factor_power_of_2 1 6553bf10ebcSSakari Ailusaux_subsamp_mono_capability 0x11c9 v1.1 6563bf10ebcSSakari Ailus- b factor_power_of_2 1 6573bf10ebcSSakari Ailusmonochrome_capability 0x11ca v1.1 6583bf10ebcSSakari Ailus- e inc_odd 0 6593bf10ebcSSakari Ailus- e inc_even 1 6603bf10ebcSSakari Ailuspixel_readout_capability 0x11cb v1.1 6613bf10ebcSSakari Ailus- e bayer 0 6623bf10ebcSSakari Ailus- e monochrome 1 6633bf10ebcSSakari Ailus- e bayer_and_mono 2 6643bf10ebcSSakari Ailusmin_even_inc_mono 0x11cc 16 v1.1 6653bf10ebcSSakari Ailusmax_even_inc_mono 0x11ce 16 v1.1 6663bf10ebcSSakari Ailusmin_odd_inc_mono 0x11d0 16 v1.1 6673bf10ebcSSakari Ailusmax_odd_inc_mono 0x11d2 16 v1.1 6683bf10ebcSSakari Ailusmin_even_inc_bc2 0x11d4 16 v1.1 6693bf10ebcSSakari Ailusmax_even_inc_bc2 0x11d6 16 v1.1 6703bf10ebcSSakari Ailusmin_odd_inc_bc2 0x11d8 16 v1.1 6713bf10ebcSSakari Ailusmax_odd_inc_bc2 0x11da 16 v1.1 6723bf10ebcSSakari Ailusmin_even_inc_mono_bc2 0x11dc 16 v1.1 6733bf10ebcSSakari Ailusmax_even_inc_mono_bc2 0x11de 16 v1.1 6743bf10ebcSSakari Ailusmin_odd_inc_mono_bc2 0x11f0 16 v1.1 6753bf10ebcSSakari Ailusmax_odd_inc_mono_bc2 0x11f2 16 v1.1 6763bf10ebcSSakari Ailus 6773bf10ebcSSakari Ailus# image scaling limit parameters 6783bf10ebcSSakari Ailusscaling_capability 0x1200 16 6793bf10ebcSSakari Ailus- e none 0 6803bf10ebcSSakari Ailus- e horizontal 1 6813bf10ebcSSakari Ailus- e reserved 2 6823bf10ebcSSakari Ailusscaler_m_min 0x1204 16 6833bf10ebcSSakari Ailusscaler_m_max 0x1206 16 6843bf10ebcSSakari Ailusscaler_n_min 0x1208 16 6853bf10ebcSSakari Ailusscaler_n_max 0x120a 16 6863bf10ebcSSakari Ailusdigital_crop_capability 0x120e 6873bf10ebcSSakari Ailus- e none 0 6883bf10ebcSSakari Ailus- e input_crop 1 6893bf10ebcSSakari Ailus 6903bf10ebcSSakari Ailus# hdr limit registers 6913bf10ebcSSakari Ailushdr_capability_1 0x1210 6923bf10ebcSSakari Ailus- b 2x2_binning 0 6933bf10ebcSSakari Ailus- b combined_analog_gain 1 6943bf10ebcSSakari Ailus- b separate_analog_gain 2 6953bf10ebcSSakari Ailus- b upscaling 3 6963bf10ebcSSakari Ailus- b reset_sync 4 6973bf10ebcSSakari Ailus- b direct_short_exp_timing 5 6983bf10ebcSSakari Ailus- b direct_short_exp_synthesis 6 6993bf10ebcSSakari Ailusmin_hdr_bit_depth 0x1211 7003bf10ebcSSakari Ailushdr_resolution_sub_types 0x1212 7013bf10ebcSSakari Ailushdr_resolution_sub_type(n) 0x1213 7023bf10ebcSSakari Ailus- l n 0 1 1 7033bf10ebcSSakari Ailus- f row 0 3 7043bf10ebcSSakari Ailus- f column 4 7 7053bf10ebcSSakari Ailushdr_capability_2 0x121b 7063bf10ebcSSakari Ailus- b combined_digital_gain 0 7073bf10ebcSSakari Ailus- b separate_digital_gain 1 7083bf10ebcSSakari Ailus- b timing_mode 3 7093bf10ebcSSakari Ailus- b synthesis_mode 4 7103bf10ebcSSakari Ailusmax_hdr_bit_depth 0x121c 7113bf10ebcSSakari Ailus 7123bf10ebcSSakari Ailus# usl capability register 7133bf10ebcSSakari Ailususl_support_capability 0x1230 v1.1 7143bf10ebcSSakari Ailus- b clock_tree 0 7153bf10ebcSSakari Ailus- b rev_clock_tree 1 7163bf10ebcSSakari Ailus- b rev_clock_calc 2 7173bf10ebcSSakari Ailususl_clock_mode_d_capability 0x1231 v1.1 7183bf10ebcSSakari Ailus- b cont_clock_standby 0 7193bf10ebcSSakari Ailus- b cont_clock_vblank 1 7203bf10ebcSSakari Ailus- b cont_clock_hblank 2 7213bf10ebcSSakari Ailus- b noncont_clock_standby 3 7223bf10ebcSSakari Ailus- b noncont_clock_vblank 4 7233bf10ebcSSakari Ailus- b noncont_clock_hblank 5 7243bf10ebcSSakari Ailusmin_op_sys_clk_div_rev 0x1234 v1.1 7253bf10ebcSSakari Ailusmax_op_sys_clk_div_rev 0x1236 v1.1 7263bf10ebcSSakari Ailusmin_op_pix_clk_div_rev 0x1238 v1.1 7273bf10ebcSSakari Ailusmax_op_pix_clk_div_rev 0x123a v1.1 7283bf10ebcSSakari Ailusmin_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal 7293bf10ebcSSakari Ailusmax_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal 7303bf10ebcSSakari Ailusmin_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal 7313bf10ebcSSakari Ailusmax_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal 7323bf10ebcSSakari Ailusmax_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal 7333bf10ebcSSakari Ailusmax_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal 7343bf10ebcSSakari Ailus 7353bf10ebcSSakari Ailus# image compression capability registers 7363bf10ebcSSakari Ailuscompression_capability 0x1300 7373bf10ebcSSakari Ailus- b dpcm_pcm_simple 0 7383bf10ebcSSakari Ailus 7393bf10ebcSSakari Ailus# test mode capability registers 7403bf10ebcSSakari Ailustest_mode_capability 0x1310 16 7413bf10ebcSSakari Ailus- b solid_color 0 7423bf10ebcSSakari Ailus- b color_bars 1 7433bf10ebcSSakari Ailus- b fade_to_grey 2 7443bf10ebcSSakari Ailus- b pn9 3 7453bf10ebcSSakari Ailus- b color_tile 5 7463bf10ebcSSakari Ailuspn9_data_format1 0x1312 7473bf10ebcSSakari Ailuspn9_data_format2 0x1313 7483bf10ebcSSakari Ailuspn9_data_format3 0x1314 7493bf10ebcSSakari Ailuspn9_data_format4 0x1315 7503bf10ebcSSakari Ailuspn9_misc_capability 0x1316 7513bf10ebcSSakari Ailus- f num_pixels 0 2 7523bf10ebcSSakari Ailus- b compression 3 7533bf10ebcSSakari Ailustest_pattern_capability 0x1317 v1.1 7543bf10ebcSSakari Ailus- b no_repeat 1 7553bf10ebcSSakari Ailuspattern_size_div_m1 0x1318 v1.1 7563bf10ebcSSakari Ailus 7573bf10ebcSSakari Ailus# fifo capability registers 7583bf10ebcSSakari Ailusfifo_support_capability 0x1502 7593bf10ebcSSakari Ailus- e none 0 7603bf10ebcSSakari Ailus- e derating 1 7613bf10ebcSSakari Ailus- e derating_overrating 2 7623bf10ebcSSakari Ailus 7633bf10ebcSSakari Ailus# csi-2 capability registers 7643bf10ebcSSakari Ailusphy_ctrl_capability 0x1600 7653bf10ebcSSakari Ailus- b auto_phy_ctl 0 7663bf10ebcSSakari Ailus- b ui_phy_ctl 1 7673bf10ebcSSakari Ailus- b dphy_time_ui_reg_1_ctl 2 7683bf10ebcSSakari Ailus- b dphy_time_ui_reg_2_ctl 3 7693bf10ebcSSakari Ailus- b dphy_time_ctl 4 7703bf10ebcSSakari Ailus- b dphy_ext_time_ui_reg_1_ctl 5 7713bf10ebcSSakari Ailus- b dphy_ext_time_ui_reg_2_ctl 6 7723bf10ebcSSakari Ailus- b dphy_ext_time_ctl 7 7733bf10ebcSSakari Ailuscsi_dphy_lane_mode_capability 0x1601 7743bf10ebcSSakari Ailus- b 1_lane 0 7753bf10ebcSSakari Ailus- b 2_lane 1 7763bf10ebcSSakari Ailus- b 3_lane 2 7773bf10ebcSSakari Ailus- b 4_lane 3 7783bf10ebcSSakari Ailus- b 5_lane 4 7793bf10ebcSSakari Ailus- b 6_lane 5 7803bf10ebcSSakari Ailus- b 7_lane 6 7813bf10ebcSSakari Ailus- b 8_lane 7 7823bf10ebcSSakari Ailuscsi_signaling_mode_capability 0x1602 7833bf10ebcSSakari Ailus- b csi_dphy 2 7843bf10ebcSSakari Ailus- b csi_cphy 3 7853bf10ebcSSakari Ailusfast_standby_capability 0x1603 7863bf10ebcSSakari Ailus- e no_frame_truncation 0 7873bf10ebcSSakari Ailus- e frame_truncation 1 7883bf10ebcSSakari Ailuscsi_address_control_capability 0x1604 7893bf10ebcSSakari Ailus- b cci_addr_change 0 7903bf10ebcSSakari Ailus- b 2nd_cci_addr 1 7913bf10ebcSSakari Ailus- b sw_changeable_2nd_cci_addr 2 7923bf10ebcSSakari Ailusdata_type_capability 0x1605 7933bf10ebcSSakari Ailus- b dpcm_programmable 0 7943bf10ebcSSakari Ailus- b bottom_embedded_dt_programmable 1 7953bf10ebcSSakari Ailus- b bottom_embedded_vc_programmable 2 7963bf10ebcSSakari Ailus- b ext_vc_range 3 7973bf10ebcSSakari Ailuscsi_cphy_lane_mode_capability 0x1606 7983bf10ebcSSakari Ailus- b 1_lane 0 7993bf10ebcSSakari Ailus- b 2_lane 1 8003bf10ebcSSakari Ailus- b 3_lane 2 8013bf10ebcSSakari Ailus- b 4_lane 3 8023bf10ebcSSakari Ailus- b 5_lane 4 8033bf10ebcSSakari Ailus- b 6_lane 5 8043bf10ebcSSakari Ailus- b 7_lane 6 8053bf10ebcSSakari Ailus- b 8_lane 7 8063bf10ebcSSakari Ailusemb_data_capability 0x1607 v1.1 8073bf10ebcSSakari Ailus- b two_bytes_per_raw16 0 8083bf10ebcSSakari Ailus- b two_bytes_per_raw20 1 8093bf10ebcSSakari Ailus- b two_bytes_per_raw24 2 8103bf10ebcSSakari Ailus- b no_one_byte_per_raw16 3 8113bf10ebcSSakari Ailus- b no_one_byte_per_raw20 4 8123bf10ebcSSakari Ailus- b no_one_byte_per_raw24 5 8133bf10ebcSSakari Ailusmax_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal 8143bf10ebcSSakari Ailus- l n 0 7 4 4,0x32 8153bf10ebcSSakari Ailustemp_sensor_capability 0x1618 8163bf10ebcSSakari Ailus- b supported 0 8173bf10ebcSSakari Ailus- b CCS_format 1 8183bf10ebcSSakari Ailus- b reset_0x80 2 8193bf10ebcSSakari Ailusmax_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal 8203bf10ebcSSakari Ailus- l n 0 7 4 4,0x30 8213bf10ebcSSakari Ailusdphy_equalization_capability 0x162b 8223bf10ebcSSakari Ailus- b equalization_ctrl 0 8233bf10ebcSSakari Ailus- b eq1 1 8243bf10ebcSSakari Ailus- b eq2 2 8253bf10ebcSSakari Ailuscphy_equalization_capability 0x162c 8263bf10ebcSSakari Ailus- b equalization_ctrl 0 8273bf10ebcSSakari Ailusdphy_preamble_capability 0x162d 8283bf10ebcSSakari Ailus- b preamble_seq_ctrl 0 8293bf10ebcSSakari Ailusdphy_ssc_capability 0x162e 8303bf10ebcSSakari Ailus- b supported 0 8313bf10ebcSSakari Ailuscphy_calibration_capability 0x162f 8323bf10ebcSSakari Ailus- b manual 0 8333bf10ebcSSakari Ailus- b manual_streaming 1 8343bf10ebcSSakari Ailus- b format_1_ctrl 2 8353bf10ebcSSakari Ailus- b format_2_ctrl 3 8363bf10ebcSSakari Ailus- b format_3_ctrl 4 8373bf10ebcSSakari Ailusdphy_calibration_capability 0x1630 8383bf10ebcSSakari Ailus- b manual 0 8393bf10ebcSSakari Ailus- b manual_streaming 1 8403bf10ebcSSakari Ailus- b alternate_seq 2 8413bf10ebcSSakari Ailusphy_ctrl_capability_2 0x1631 8423bf10ebcSSakari Ailus- b tgr_length 0 8433bf10ebcSSakari Ailus- b tgr_preamble_prog_seq 1 8443bf10ebcSSakari Ailus- b extra_cphy_manual_timing 2 8453bf10ebcSSakari Ailus- b clock_based_manual_cdphy 3 8463bf10ebcSSakari Ailus- b clock_based_manual_dphy 4 8473bf10ebcSSakari Ailus- b clock_based_manual_cphy 5 8483bf10ebcSSakari Ailus- b manual_lp_dphy 6 8493bf10ebcSSakari Ailus- b manual_lp_cphy 7 8503bf10ebcSSakari Ailuslrte_cphy_capability 0x1632 8513bf10ebcSSakari Ailus- b pdq_short 0 8523bf10ebcSSakari Ailus- b spacer_short 1 8533bf10ebcSSakari Ailus- b pdq_long 2 8543bf10ebcSSakari Ailus- b spacer_long 3 8553bf10ebcSSakari Ailus- b spacer_no_pdq 4 8563bf10ebcSSakari Ailuslrte_dphy_capability 0x1633 8573bf10ebcSSakari Ailus- b pdq_short_opt1 0 8583bf10ebcSSakari Ailus- b spacer_short_opt1 1 8593bf10ebcSSakari Ailus- b pdq_long_opt1 2 8603bf10ebcSSakari Ailus- b spacer_long_opt1 3 8613bf10ebcSSakari Ailus- b spacer_short_opt2 4 8623bf10ebcSSakari Ailus- b spacer_long_opt2 5 8633bf10ebcSSakari Ailus- b spacer_no_pdq_opt1 6 8643bf10ebcSSakari Ailus- b spacer_variable_opt2 7 8653bf10ebcSSakari Ailusalps_capability_dphy 0x1634 8663bf10ebcSSakari Ailus- e lvlp_not_supported 0 0x3 8673bf10ebcSSakari Ailus- e lvlp_supported 1 0x3 8683bf10ebcSSakari Ailus- e controllable_lvlp 2 0x3 8693bf10ebcSSakari Ailusalps_capability_cphy 0x1635 8703bf10ebcSSakari Ailus- e lvlp_not_supported 0 0x3 8713bf10ebcSSakari Ailus- e lvlp_supported 1 0x3 8723bf10ebcSSakari Ailus- e controllable_lvlp 2 0x3 8733bf10ebcSSakari Ailus- e alp_not_supported 0xc 0xc 8743bf10ebcSSakari Ailus- e alp_supported 0xd 0xc 8753bf10ebcSSakari Ailus- e controllable_alp 0xe 0xc 8763bf10ebcSSakari Ailusscrambling_capability 0x1636 8773bf10ebcSSakari Ailus- b scrambling_supported 0 8783bf10ebcSSakari Ailus- f max_seeds_per_lane_c 1 2 8793bf10ebcSSakari Ailus- e 1 0 8803bf10ebcSSakari Ailus- e 4 3 8813bf10ebcSSakari Ailus- f num_seed_regs 3 5 8823bf10ebcSSakari Ailus- e 0 0 8833bf10ebcSSakari Ailus- e 1 1 8843bf10ebcSSakari Ailus- e 4 4 8853bf10ebcSSakari Ailus- b num_seed_per_lane 6 8863bf10ebcSSakari Ailusdphy_manual_constant 0x1637 8873bf10ebcSSakari Ailuscphy_manual_constant 0x1638 8883bf10ebcSSakari AilusCSI2_interface_capability_misc 0x1639 v1.1 8893bf10ebcSSakari Ailus- b eotp_short_pkt_opt2 0 8903bf10ebcSSakari AilusPHY_ctrl_capability_3 0x165c v1.1 8913bf10ebcSSakari Ailus- b dphy_timing_not_multiple 0 8923bf10ebcSSakari Ailus- b dphy_min_timing_value_1 1 8933bf10ebcSSakari Ailus- b twakeup_supported 2 8943bf10ebcSSakari Ailus- b tinit_supported 3 8953bf10ebcSSakari Ailus- b ths_exit_supported 4 8963bf10ebcSSakari Ailus- b cphy_timing_not_multiple 5 8973bf10ebcSSakari Ailus- b cphy_min_timing_value_1 6 8983bf10ebcSSakari Ailusdphy_sf 0x165d v1.1 8993bf10ebcSSakari Ailuscphy_sf 0x165e v1.1 9003bf10ebcSSakari Ailus- f twakeup 0 3 9013bf10ebcSSakari Ailus- f tinit 4 7 9023bf10ebcSSakari Ailusdphy_limits_1 0x165f v1.1 9033bf10ebcSSakari Ailus- f ths_prepare 0 3 9043bf10ebcSSakari Ailus- f ths_zero 4 7 9053bf10ebcSSakari Ailusdphy_limits_2 0x1660 v1.1 9063bf10ebcSSakari Ailus- f ths_trail 0 3 9073bf10ebcSSakari Ailus- f tclk_trail_min 4 7 9083bf10ebcSSakari Ailusdphy_limits_3 0x1661 v1.1 9093bf10ebcSSakari Ailus- f tclk_prepare 0 3 9103bf10ebcSSakari Ailus- f tclk_zero 4 7 9113bf10ebcSSakari Ailusdphy_limits_4 0x1662 v1.1 9123bf10ebcSSakari Ailus- f tclk_post 0 3 9133bf10ebcSSakari Ailus- f tlpx 4 7 9143bf10ebcSSakari Ailusdphy_limits_5 0x1663 v1.1 9153bf10ebcSSakari Ailus- f ths_exit 0 3 9163bf10ebcSSakari Ailus- f twakeup 4 7 9173bf10ebcSSakari Ailusdphy_limits_6 0x1664 v1.1 9183bf10ebcSSakari Ailus- f tinit 0 3 9193bf10ebcSSakari Ailuscphy_limits_1 0x1665 v1.1 9203bf10ebcSSakari Ailus- f t3_prepare_max 0 3 9213bf10ebcSSakari Ailus- f t3_lpx_max 4 7 9223bf10ebcSSakari Ailuscphy_limits_2 0x1666 v1.1 9233bf10ebcSSakari Ailus- f ths_exit_max 0 3 9243bf10ebcSSakari Ailus- f twakeup_max 4 7 9253bf10ebcSSakari Ailuscphy_limits_3 0x1667 v1.1 9263bf10ebcSSakari Ailus- f tinit_max 0 3 9273bf10ebcSSakari Ailus 9283bf10ebcSSakari Ailus# binning capability registers 9293bf10ebcSSakari Ailusmin_frame_length_lines_bin 0x1700 16 9303bf10ebcSSakari Ailusmax_frame_length_lines_bin 0x1702 16 9313bf10ebcSSakari Ailusmin_line_length_pck_bin 0x1704 16 9323bf10ebcSSakari Ailusmax_line_length_pck_bin 0x1706 16 9333bf10ebcSSakari Ailusmin_line_blanking_pck_bin 0x1708 16 9343bf10ebcSSakari Ailusfine_integration_time_min_bin 0x170a 16 9353bf10ebcSSakari Ailusfine_integration_time_max_margin_bin 0x170c 16 9363bf10ebcSSakari Ailusbinning_capability 0x1710 9373bf10ebcSSakari Ailus- e unsupported 0 9383bf10ebcSSakari Ailus- e binning_then_subsampling 1 9393bf10ebcSSakari Ailus- e subsampling_then_binning 2 9403bf10ebcSSakari Ailusbinning_weighting_capability 0x1711 9413bf10ebcSSakari Ailus- b averaged 0 9423bf10ebcSSakari Ailus- b summed 1 9433bf10ebcSSakari Ailus- b bayer_corrected 2 9443bf10ebcSSakari Ailus- b module_specific_weight 3 9453bf10ebcSSakari Ailusbinning_sub_types 0x1712 9463bf10ebcSSakari Ailusbinning_sub_type(n) 0x1713 9473bf10ebcSSakari Ailus- l n 0 63 1 9483bf10ebcSSakari Ailus- f row 0 3 9493bf10ebcSSakari Ailus- f column 4 7 9503bf10ebcSSakari Ailusbinning_weighting_mono_capability 0x1771 v1.1 9513bf10ebcSSakari Ailus- b averaged 0 9523bf10ebcSSakari Ailus- b summed 1 9533bf10ebcSSakari Ailus- b bayer_corrected 2 9543bf10ebcSSakari Ailus- b module_specific_weight 3 9553bf10ebcSSakari Ailusbinning_sub_types_mono 0x1772 v1.1 9563bf10ebcSSakari Ailusbinning_sub_type_mono(n) 0x1773 v1.1 f 9573bf10ebcSSakari Ailus- l n 0 63 1 9583bf10ebcSSakari Ailus 9593bf10ebcSSakari Ailus# data transfer interface capability registers 9603bf10ebcSSakari Ailusdata_transfer_if_capability 0x1800 9613bf10ebcSSakari Ailus- b supported 0 9623bf10ebcSSakari Ailus- b polling 2 9633bf10ebcSSakari Ailus 9643bf10ebcSSakari Ailus# sensor correction capability registers 9653bf10ebcSSakari Ailusshading_correction_capability 0x1900 9663bf10ebcSSakari Ailus- b color_shading 0 9673bf10ebcSSakari Ailus- b luminance_correction 1 9683bf10ebcSSakari Ailusgreen_imbalance_capability 0x1901 9693bf10ebcSSakari Ailus- b supported 0 9703bf10ebcSSakari Ailusmodule_specific_correction_capability 0x1903 9713bf10ebcSSakari Ailusdefect_correction_capability 0x1904 16 9723bf10ebcSSakari Ailus- b mapped_defect 0 9733bf10ebcSSakari Ailus- b dynamic_couplet 2 9743bf10ebcSSakari Ailus- b dynamic_single 5 9753bf10ebcSSakari Ailus- b combined_dynamic 8 9763bf10ebcSSakari Ailusdefect_correction_capability_2 0x1906 16 9773bf10ebcSSakari Ailus- b dynamic_triplet 3 9783bf10ebcSSakari Ailusnf_capability 0x1908 9793bf10ebcSSakari Ailus- b luma 0 9803bf10ebcSSakari Ailus- b chroma 1 9813bf10ebcSSakari Ailus- b combined 2 9823bf10ebcSSakari Ailus 9833bf10ebcSSakari Ailus# optical black readout capability registers 9843bf10ebcSSakari Ailusob_readout_capability 0x1980 9853bf10ebcSSakari Ailus- b controllable_readout 0 9863bf10ebcSSakari Ailus- b visible_pixel_readout 1 9873bf10ebcSSakari Ailus- b different_vc_readout 2 9883bf10ebcSSakari Ailus- b different_dt_readout 3 9893bf10ebcSSakari Ailus- b prog_data_format 4 9903bf10ebcSSakari Ailus 9913bf10ebcSSakari Ailus# color feedback capability registers 9923bf10ebcSSakari Ailuscolor_feedback_capability 0x1987 9933bf10ebcSSakari Ailus- b kelvin 0 9943bf10ebcSSakari Ailus- b awb_gain 1 9953bf10ebcSSakari Ailus 9963bf10ebcSSakari Ailus# cfa pattern capability registers 9973bf10ebcSSakari AilusCFA_pattern_capability 0x1990 v1.1 9983bf10ebcSSakari Ailus- e bayer 0 9993bf10ebcSSakari Ailus- e monochrome 1 10003bf10ebcSSakari Ailus- e 4x4_quad_bayer 2 10013bf10ebcSSakari Ailus- e vendor_specific 3 10023bf10ebcSSakari AilusCFA_pattern_conversion_capability 0x1991 v1.1 10033bf10ebcSSakari Ailus- b bayer 0 10043bf10ebcSSakari Ailus 10053bf10ebcSSakari Ailus# timer capability registers 10063bf10ebcSSakari Ailusflash_mode_capability 0x1a02 10073bf10ebcSSakari Ailus- b single_strobe 0 10083bf10ebcSSakari Ailussa_strobe_mode_capability 0x1a03 10093bf10ebcSSakari Ailus- b fixed_width 0 10103bf10ebcSSakari Ailus- b edge_ctrl 1 10113bf10ebcSSakari Ailus 10123bf10ebcSSakari Ailus# soft reset capability registers 10133bf10ebcSSakari Ailusreset_max_delay 0x1a10 v1.1 10143bf10ebcSSakari Ailusreset_min_time 0x1a11 v1.1 10153bf10ebcSSakari Ailus 10163bf10ebcSSakari Ailus# pdaf capability registers 10173bf10ebcSSakari Ailuspdaf_capability_1 0x1b80 10183bf10ebcSSakari Ailus- b supported 0 10193bf10ebcSSakari Ailus- b processed_bottom_embedded 1 10203bf10ebcSSakari Ailus- b processed_interleaved 2 10213bf10ebcSSakari Ailus- b raw_bottom_embedded 3 10223bf10ebcSSakari Ailus- b raw_interleaved 4 10233bf10ebcSSakari Ailus- b visible_pdaf_correction 5 10243bf10ebcSSakari Ailus- b vc_interleaving 6 10253bf10ebcSSakari Ailus- b dt_interleaving 7 10263bf10ebcSSakari Ailuspdaf_capability_2 0x1b81 10273bf10ebcSSakari Ailus- b ROI 0 10283bf10ebcSSakari Ailus- b after_digital_crop 1 10293bf10ebcSSakari Ailus- b ctrl_retimed 2 10303bf10ebcSSakari Ailus 10313bf10ebcSSakari Ailus# bracketing interface capability registers 10323bf10ebcSSakari Ailusbracketing_lut_capability_1 0x1c00 10333bf10ebcSSakari Ailus- b coarse_integration 0 10343bf10ebcSSakari Ailus- b global_analog_gain 1 10353bf10ebcSSakari Ailus- b flash 4 10363bf10ebcSSakari Ailus- b global_digital_gain 5 10373bf10ebcSSakari Ailus- b alternate_global_analog_gain 6 10383bf10ebcSSakari Ailusbracketing_lut_capability_2 0x1c01 10393bf10ebcSSakari Ailus- b single_bracketing_mode 0 10403bf10ebcSSakari Ailus- b looped_bracketing_mode 1 10413bf10ebcSSakari Ailusbracketing_lut_size 0x1c02 1042