1.. SPDX-License-Identifier: GPL-2.0 2 3===================================== 4Generic System Interconnect Subsystem 5===================================== 6 7Introduction 8------------ 9 10This framework is designed to provide a standard kernel interface to control 11the settings of the interconnects on an SoC. These settings can be throughput, 12latency and priority between multiple interconnected devices or functional 13blocks. This can be controlled dynamically in order to save power or provide 14maximum performance. 15 16The interconnect bus is hardware with configurable parameters, which can be 17set on a data path according to the requests received from various drivers. 18An example of interconnect buses are the interconnects between various 19components or functional blocks in chipsets. There can be multiple interconnects 20on an SoC that can be multi-tiered. 21 22Below is a simplified diagram of a real-world SoC interconnect bus topology. 23 24:: 25 26 +----------------+ +----------------+ 27 | HW Accelerator |--->| M NoC |<---------------+ 28 +----------------+ +----------------+ | 29 | | +------------+ 30 +-----+ +-------------+ V +------+ | | 31 | DDR | | +--------+ | PCIe | | | 32 +-----+ | | Slaves | +------+ | | 33 ^ ^ | +--------+ | | C NoC | 34 | | V V | | 35 +------------------+ +------------------------+ | | +-----+ 36 | |-->| |-->| |-->| CPU | 37 | |-->| |<--| | +-----+ 38 | Mem NoC | | S NoC | +------------+ 39 | |<--| |---------+ | 40 | |<--| |<------+ | | +--------+ 41 +------------------+ +------------------------+ | | +-->| Slaves | 42 ^ ^ ^ ^ ^ | | +--------+ 43 | | | | | | V 44 +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+ 45 | CPUs | | | GPU | | DSP | | Masters |-->| P NoC |-->| Slaves | 46 +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+ 47 | 48 +-------+ 49 | Modem | 50 +-------+ 51 52Terminology 53----------- 54 55Interconnect provider is the software definition of the interconnect hardware. 56The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC 57and Mem NoC. 58 59Interconnect node is the software definition of the interconnect hardware 60port. Each interconnect provider consists of multiple interconnect nodes, 61which are connected to other SoC components including other interconnect 62providers. The point on the diagram where the CPUs connect to the memory is 63called an interconnect node, which belongs to the Mem NoC interconnect provider. 64 65Interconnect endpoints are the first or the last element of the path. Every 66endpoint is a node, but not every node is an endpoint. 67 68Interconnect path is everything between two endpoints including all the nodes 69that have to be traversed to reach from a source to destination node. It may 70include multiple master-slave pairs across several interconnect providers. 71 72Interconnect consumers are the entities which make use of the data paths exposed 73by the providers. The consumers send requests to providers requesting various 74throughput, latency and priority. Usually the consumers are device drivers, that 75send request based on their needs. An example for a consumer is a video decoder 76that supports various formats and image sizes. 77 78Interconnect providers 79---------------------- 80 81Interconnect provider is an entity that implements methods to initialize and 82configure interconnect bus hardware. The interconnect provider drivers should 83be registered with the interconnect provider core. 84 85.. kernel-doc:: include/linux/interconnect-provider.h 86 87Interconnect consumers 88---------------------- 89 90Interconnect consumers are the clients which use the interconnect APIs to 91get paths between endpoints and set their bandwidth/latency/QoS requirements 92for these interconnect paths. These interfaces are not currently 93documented. 94