1fbbe0bffSVinod Koul============================== 2fbbe0bffSVinod KoulPXA/MMP - DMA Slave controller 3fbbe0bffSVinod Koul============================== 4fbbe0bffSVinod Koul 5fbbe0bffSVinod KoulConstraints 6fbbe0bffSVinod Koul=========== 7fbbe0bffSVinod Koul 8fbbe0bffSVinod Koula) Transfers hot queuing 9fbbe0bffSVinod KoulA driver submitting a transfer and issuing it should be granted the transfer 10fbbe0bffSVinod Koulis queued even on a running DMA channel. 11fbbe0bffSVinod KoulThis implies that the queuing doesn't wait for the previous transfer end, 12fbbe0bffSVinod Kouland that the descriptor chaining is not only done in the irq/tasklet code 13fbbe0bffSVinod Koultriggered by the end of the transfer. 14fbbe0bffSVinod KoulA transfer which is submitted and issued on a phy doesn't wait for a phy to 15fbbe0bffSVinod Koulstop and restart, but is submitted on a "running channel". The other 16fbbe0bffSVinod Kouldrivers, especially mmp_pdma waited for the phy to stop before relaunching 17fbbe0bffSVinod Koula new transfer. 18fbbe0bffSVinod Koul 19fbbe0bffSVinod Koulb) All transfers having asked for confirmation should be signaled 20fbbe0bffSVinod KoulAny issued transfer with DMA_PREP_INTERRUPT should trigger a callback call. 21fbbe0bffSVinod KoulThis implies that even if an irq/tasklet is triggered by end of tx1, but 22fbbe0bffSVinod Koulat the time of irq/dma tx2 is already finished, tx1->complete() and 23fbbe0bffSVinod Koultx2->complete() should be called. 24fbbe0bffSVinod Koul 25fbbe0bffSVinod Koulc) Channel running state 26fbbe0bffSVinod KoulA driver should be able to query if a channel is running or not. For the 27fbbe0bffSVinod Koulmultimedia case, such as video capture, if a transfer is submitted and then 28fbbe0bffSVinod Koula check of the DMA channel reports a "stopped channel", the transfer should 29fbbe0bffSVinod Koulnot be issued until the next "start of frame interrupt", hence the need to 30fbbe0bffSVinod Koulknow if a channel is in running or stopped state. 31fbbe0bffSVinod Koul 32fbbe0bffSVinod Kould) Bandwidth guarantee 33fbbe0bffSVinod KoulThe PXA architecture has 4 levels of DMAs priorities : high, normal, low. 34fbbe0bffSVinod KoulThe high priorities get twice as much bandwidth as the normal, which get twice 35fbbe0bffSVinod Koulas much as the low priorities. 36fbbe0bffSVinod KoulA driver should be able to request a priority, especially the real-time 37fbbe0bffSVinod Koulones such as pxa_camera with (big) throughputs. 38fbbe0bffSVinod Koul 39fbbe0bffSVinod KoulDesign 40fbbe0bffSVinod Koul====== 41fbbe0bffSVinod Koula) Virtual channels 42fbbe0bffSVinod KoulSame concept as in sa11x0 driver, ie. a driver was assigned a "virtual 43fbbe0bffSVinod Koulchannel" linked to the requestor line, and the physical DMA channel is 44fbbe0bffSVinod Koulassigned on the fly when the transfer is issued. 45fbbe0bffSVinod Koul 46fbbe0bffSVinod Koulb) Transfer anatomy for a scatter-gather transfer 47fbbe0bffSVinod Koul 48fbbe0bffSVinod Koul:: 49fbbe0bffSVinod Koul 50fbbe0bffSVinod Koul +------------+-----+---------------+----------------+-----------------+ 51fbbe0bffSVinod Koul | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker | 52fbbe0bffSVinod Koul +------------+-----+---------------+----------------+-----------------+ 53fbbe0bffSVinod Koul 54fbbe0bffSVinod KoulThis structure is pointed by dma->sg_cpu. 55fbbe0bffSVinod KoulThe descriptors are used as follows : 56fbbe0bffSVinod Koul 57fbbe0bffSVinod Koul - desc-sg[i]: i-th descriptor, transferring the i-th sg 58fbbe0bffSVinod Koul element to the video buffer scatter gather 59fbbe0bffSVinod Koul 60fbbe0bffSVinod Koul - status updater 61fbbe0bffSVinod Koul Transfers a single u32 to a well known dma coherent memory to leave 62fbbe0bffSVinod Koul a trace that this transfer is done. The "well known" is unique per 63fbbe0bffSVinod Koul physical channel, meaning that a read of this value will tell which 64fbbe0bffSVinod Koul is the last finished transfer at that point in time. 65fbbe0bffSVinod Koul 66fbbe0bffSVinod Koul - finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN 67fbbe0bffSVinod Koul 68fbbe0bffSVinod Koul - linker: has ddadr= desc-sg[0] of next transfer, dcmd=0 69fbbe0bffSVinod Koul 70fbbe0bffSVinod Koulc) Transfers hot-chaining 71fbbe0bffSVinod KoulSuppose the running chain is: 72fbbe0bffSVinod Koul 73fbbe0bffSVinod Koul:: 74fbbe0bffSVinod Koul 75fbbe0bffSVinod Koul Buffer 1 Buffer 2 76fbbe0bffSVinod Koul +---------+----+---+ +----+----+----+---+ 77fbbe0bffSVinod Koul | d0 | .. | dN | l | | d0 | .. | dN | f | 78fbbe0bffSVinod Koul +---------+----+-|-+ ^----+----+----+---+ 79fbbe0bffSVinod Koul | | 80fbbe0bffSVinod Koul +----+ 81fbbe0bffSVinod Koul 82fbbe0bffSVinod KoulAfter a call to dmaengine_submit(b3), the chain will look like: 83fbbe0bffSVinod Koul 84fbbe0bffSVinod Koul:: 85fbbe0bffSVinod Koul 86fbbe0bffSVinod Koul Buffer 1 Buffer 2 Buffer 3 87fbbe0bffSVinod Koul +---------+----+---+ +----+----+----+---+ +----+----+----+---+ 88fbbe0bffSVinod Koul | d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f | 89fbbe0bffSVinod Koul +---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+ 90fbbe0bffSVinod Koul | | | | 91fbbe0bffSVinod Koul +----+ +----+ 92fbbe0bffSVinod Koul new_link 93fbbe0bffSVinod Koul 94fbbe0bffSVinod KoulIf while new_link was created the DMA channel stopped, it is _not_ 95fbbe0bffSVinod Koulrestarted. Hot-chaining doesn't break the assumption that 96fbbe0bffSVinod Kouldma_async_issue_pending() is to be used to ensure the transfer is actually started. 97fbbe0bffSVinod Koul 98fbbe0bffSVinod KoulOne exception to this rule : 99fbbe0bffSVinod Koul 100fbbe0bffSVinod Koul- if Buffer1 and Buffer2 had all their addresses 8 bytes aligned 101fbbe0bffSVinod Koul 102fbbe0bffSVinod Koul- and if Buffer3 has at least one address not 4 bytes aligned 103fbbe0bffSVinod Koul 104fbbe0bffSVinod Koul- then hot-chaining cannot happen, as the channel must be stopped, the 105fbbe0bffSVinod Koul "align bit" must be set, and the channel restarted As a consequence, 106fbbe0bffSVinod Koul such a transfer tx_submit() will be queued on the submitted queue, and 107fbbe0bffSVinod Koul this specific case if the DMA is already running in aligned mode. 108fbbe0bffSVinod Koul 109fbbe0bffSVinod Kould) Transfers completion updater 110fbbe0bffSVinod KoulEach time a transfer is completed on a channel, an interrupt might be 111fbbe0bffSVinod Koulgenerated or not, up to the client's request. But in each case, the last 112fbbe0bffSVinod Kouldescriptor of a transfer, the "status updater", will write the latest 113fbbe0bffSVinod Koultransfer being completed into the physical channel's completion mark. 114fbbe0bffSVinod Koul 115fbbe0bffSVinod KoulThis will speed up residue calculation, for large transfers such as video 116fbbe0bffSVinod Koulbuffers which hold around 6k descriptors or more. This also allows without 117fbbe0bffSVinod Koulany lock to find out what is the latest completed transfer in a running 118fbbe0bffSVinod KoulDMA chain. 119fbbe0bffSVinod Koul 120fbbe0bffSVinod Koule) Transfers completion, irq and tasklet 121fbbe0bffSVinod KoulWhen a transfer flagged as "DMA_PREP_INTERRUPT" is finished, the dma irq 122fbbe0bffSVinod Koulis raised. Upon this interrupt, a tasklet is scheduled for the physical 123fbbe0bffSVinod Koulchannel. 124fbbe0bffSVinod Koul 125fbbe0bffSVinod KoulThe tasklet is responsible for : 126fbbe0bffSVinod Koul 127fbbe0bffSVinod Koul- reading the physical channel last updater mark 128fbbe0bffSVinod Koul 129fbbe0bffSVinod Koul- calling all the transfer callbacks of finished transfers, based on 130fbbe0bffSVinod Koul that mark, and each transfer flags. 131fbbe0bffSVinod Koul 132fbbe0bffSVinod KoulIf a transfer is completed while this handling is done, a dma irq will 133fbbe0bffSVinod Koulbe raised, and the tasklet will be scheduled once again, having a new 134fbbe0bffSVinod Koulupdater mark. 135fbbe0bffSVinod Koul 136fbbe0bffSVinod Koulf) Residue 137fbbe0bffSVinod KoulResidue granularity will be descriptor based. The issued but not completed 138fbbe0bffSVinod Koultransfers will be scanned for all of their descriptors against the 139fbbe0bffSVinod Koulcurrently running descriptor. 140fbbe0bffSVinod Koul 141fbbe0bffSVinod Koulg) Most complicated case of driver's tx queues 142fbbe0bffSVinod KoulThe most tricky situation is when : 143fbbe0bffSVinod Koul 144fbbe0bffSVinod Koul - there are not "acked" transfers (tx0) 145fbbe0bffSVinod Koul 146fbbe0bffSVinod Koul - a driver submitted an aligned tx1, not chained 147fbbe0bffSVinod Koul 148fbbe0bffSVinod Koul - a driver submitted an aligned tx2 => tx2 is cold chained to tx1 149fbbe0bffSVinod Koul 150fbbe0bffSVinod Koul - a driver issued tx1+tx2 => channel is running in aligned mode 151fbbe0bffSVinod Koul 152fbbe0bffSVinod Koul - a driver submitted an aligned tx3 => tx3 is hot-chained 153fbbe0bffSVinod Koul 154fbbe0bffSVinod Koul - a driver submitted an unaligned tx4 => tx4 is put in submitted queue, 155fbbe0bffSVinod Koul not chained 156fbbe0bffSVinod Koul 157fbbe0bffSVinod Koul - a driver issued tx4 => tx4 is put in issued queue, not chained 158fbbe0bffSVinod Koul 159fbbe0bffSVinod Koul - a driver submitted an aligned tx5 => tx5 is put in submitted queue, not 160fbbe0bffSVinod Koul chained 161fbbe0bffSVinod Koul 162fbbe0bffSVinod Koul - a driver submitted an aligned tx6 => tx6 is put in submitted queue, 163fbbe0bffSVinod Koul cold chained to tx5 164fbbe0bffSVinod Koul 165fbbe0bffSVinod Koul This translates into (after tx4 is issued) : 166fbbe0bffSVinod Koul 167fbbe0bffSVinod Koul - issued queue 168fbbe0bffSVinod Koul 169fbbe0bffSVinod Koul :: 170fbbe0bffSVinod Koul 171fbbe0bffSVinod Koul +-----+ +-----+ +-----+ +-----+ 172fbbe0bffSVinod Koul | tx1 | | tx2 | | tx3 | | tx4 | 173fbbe0bffSVinod Koul +---|-+ ^---|-+ ^-----+ +-----+ 174fbbe0bffSVinod Koul | | | | 175fbbe0bffSVinod Koul +---+ +---+ 176fbbe0bffSVinod Koul - submitted queue 177fbbe0bffSVinod Koul +-----+ +-----+ 178fbbe0bffSVinod Koul | tx5 | | tx6 | 179fbbe0bffSVinod Koul +---|-+ ^-----+ 180fbbe0bffSVinod Koul | | 181fbbe0bffSVinod Koul +---+ 182fbbe0bffSVinod Koul 183fbbe0bffSVinod Koul- completed queue : empty 184fbbe0bffSVinod Koul 185fbbe0bffSVinod Koul- allocated queue : tx0 186fbbe0bffSVinod Koul 187fbbe0bffSVinod KoulIt should be noted that after tx3 is completed, the channel is stopped, and 188fbbe0bffSVinod Koulrestarted in "unaligned mode" to handle tx4. 189fbbe0bffSVinod Koul 190fbbe0bffSVinod KoulAuthor: Robert Jarzmik <robert.jarzmik@free.fr> 191