1================================== 2DMAengine controller documentation 3================================== 4 5Hardware Introduction 6===================== 7 8Most of the Slave DMA controllers have the same general principles of 9operations. 10 11They have a given number of channels to use for the DMA transfers, and 12a given number of requests lines. 13 14Requests and channels are pretty much orthogonal. Channels can be used 15to serve several to any requests. To simplify, channels are the 16entities that will be doing the copy, and requests what endpoints are 17involved. 18 19The request lines actually correspond to physical lines going from the 20DMA-eligible devices to the controller itself. Whenever the device 21will want to start a transfer, it will assert a DMA request (DRQ) by 22asserting that request line. 23 24A very simple DMA controller would only take into account a single 25parameter: the transfer size. At each clock cycle, it would transfer a 26byte of data from one buffer to another, until the transfer size has 27been reached. 28 29That wouldn't work well in the real world, since slave devices might 30require a specific number of bits to be transferred in a single 31cycle. For example, we may want to transfer as much data as the 32physical bus allows to maximize performances when doing a simple 33memory copy operation, but our audio device could have a narrower FIFO 34that requires data to be written exactly 16 or 24 bits at a time. This 35is why most if not all of the DMA controllers can adjust this, using a 36parameter called the transfer width. 37 38Moreover, some DMA controllers, whenever the RAM is used as a source 39or destination, can group the reads or writes in memory into a buffer, 40so instead of having a lot of small memory accesses, which is not 41really efficient, you'll get several bigger transfers. This is done 42using a parameter called the burst size, that defines how many single 43reads/writes it's allowed to do without the controller splitting the 44transfer into smaller sub-transfers. 45 46Our theoretical DMA controller would then only be able to do transfers 47that involve a single contiguous block of data. However, some of the 48transfers we usually have are not, and want to copy data from 49non-contiguous buffers to a contiguous buffer, which is called 50scatter-gather. 51 52DMAEngine, at least for mem2dev transfers, require support for 53scatter-gather. So we're left with two cases here: either we have a 54quite simple DMA controller that doesn't support it, and we'll have to 55implement it in software, or we have a more advanced DMA controller, 56that implements in hardware scatter-gather. 57 58The latter are usually programmed using a collection of chunks to 59transfer, and whenever the transfer is started, the controller will go 60over that collection, doing whatever we programmed there. 61 62This collection is usually either a table or a linked list. You will 63then push either the address of the table and its number of elements, 64or the first item of the list to one channel of the DMA controller, 65and whenever a DRQ will be asserted, it will go through the collection 66to know where to fetch the data from. 67 68Either way, the format of this collection is completely dependent on 69your hardware. Each DMA controller will require a different structure, 70but all of them will require, for every chunk, at least the source and 71destination addresses, whether it should increment these addresses or 72not and the three parameters we saw earlier: the burst size, the 73transfer width and the transfer size. 74 75The one last thing is that usually, slave devices won't issue DRQ by 76default, and you have to enable this in your slave device driver first 77whenever you're willing to use DMA. 78 79These were just the general memory-to-memory (also called mem2mem) or 80memory-to-device (mem2dev) kind of transfers. Most devices often 81support other kind of transfers or memory operations that dmaengine 82support and will be detailed later in this document. 83 84DMA Support in Linux 85==================== 86 87Historically, DMA controller drivers have been implemented using the 88async TX API, to offload operations such as memory copy, XOR, 89cryptography, etc., basically any memory to memory operation. 90 91Over time, the need for memory to device transfers arose, and 92dmaengine was extended. Nowadays, the async TX API is written as a 93layer on top of dmaengine, and acts as a client. Still, dmaengine 94accommodates that API in some cases, and made some design choices to 95ensure that it stayed compatible. 96 97For more information on the Async TX API, please look the relevant 98documentation file in Documentation/crypto/async-tx-api.txt. 99 100DMAEngine APIs 101============== 102 103``struct dma_device`` Initialization 104------------------------------------ 105 106Just like any other kernel framework, the whole DMAEngine registration 107relies on the driver filling a structure and registering against the 108framework. In our case, that structure is dma_device. 109 110The first thing you need to do in your driver is to allocate this 111structure. Any of the usual memory allocators will do, but you'll also 112need to initialize a few fields in there: 113 114- channels: should be initialized as a list using the 115 INIT_LIST_HEAD macro for example 116 117- src_addr_widths: 118 should contain a bitmask of the supported source transfer width 119 120- dst_addr_widths: 121 should contain a bitmask of the supported destination transfer width 122 123- directions: 124 should contain a bitmask of the supported slave directions 125 (i.e. excluding mem2mem transfers) 126 127- residue_granularity: 128 129 - Granularity of the transfer residue reported to dma_set_residue. 130 This can be either: 131 132 - Descriptor 133 134 - Your device doesn't support any kind of residue 135 reporting. The framework will only know that a particular 136 transaction descriptor is done. 137 138 - Segment 139 140 - Your device is able to report which chunks have been transferred 141 142 - Burst 143 144 - Your device is able to report which burst have been transferred 145 146 - dev: should hold the pointer to the ``struct device`` associated 147 to your current driver instance. 148 149Supported transaction types 150--------------------------- 151 152The next thing you need is to set which transaction types your device 153(and driver) supports. 154 155Our ``dma_device structure`` has a field called cap_mask that holds the 156various types of transaction supported, and you need to modify this 157mask using the dma_cap_set function, with various flags depending on 158transaction types you support as an argument. 159 160All those capabilities are defined in the ``dma_transaction_type enum``, 161in ``include/linux/dmaengine.h`` 162 163Currently, the types available are: 164 165- DMA_MEMCPY 166 167 - The device is able to do memory to memory copies 168 169- DMA_XOR 170 171 - The device is able to perform XOR operations on memory areas 172 173 - Used to accelerate XOR intensive tasks, such as RAID5 174 175- DMA_XOR_VAL 176 177 - The device is able to perform parity check using the XOR 178 algorithm against a memory buffer. 179 180- DMA_PQ 181 182 - The device is able to perform RAID6 P+Q computations, P being a 183 simple XOR, and Q being a Reed-Solomon algorithm. 184 185- DMA_PQ_VAL 186 187 - The device is able to perform parity check using RAID6 P+Q 188 algorithm against a memory buffer. 189 190- DMA_INTERRUPT 191 192 - The device is able to trigger a dummy transfer that will 193 generate periodic interrupts 194 195 - Used by the client drivers to register a callback that will be 196 called on a regular basis through the DMA controller interrupt 197 198- DMA_PRIVATE 199 200 - The devices only supports slave transfers, and as such isn't 201 available for async transfers. 202 203- DMA_ASYNC_TX 204 205 - Must not be set by the device, and will be set by the framework 206 if needed 207 208 - TODO: What is it about? 209 210- DMA_SLAVE 211 212 - The device can handle device to memory transfers, including 213 scatter-gather transfers. 214 215 - While in the mem2mem case we were having two distinct types to 216 deal with a single chunk to copy or a collection of them, here, 217 we just have a single transaction type that is supposed to 218 handle both. 219 220 - If you want to transfer a single contiguous memory buffer, 221 simply build a scatter list with only one item. 222 223- DMA_CYCLIC 224 225 - The device can handle cyclic transfers. 226 227 - A cyclic transfer is a transfer where the chunk collection will 228 loop over itself, with the last item pointing to the first. 229 230 - It's usually used for audio transfers, where you want to operate 231 on a single ring buffer that you will fill with your audio data. 232 233- DMA_INTERLEAVE 234 235 - The device supports interleaved transfer. 236 237 - These transfers can transfer data from a non-contiguous buffer 238 to a non-contiguous buffer, opposed to DMA_SLAVE that can 239 transfer data from a non-contiguous data set to a continuous 240 destination buffer. 241 242 - It's usually used for 2d content transfers, in which case you 243 want to transfer a portion of uncompressed data directly to the 244 display to print it 245 246These various types will also affect how the source and destination 247addresses change over time. 248 249Addresses pointing to RAM are typically incremented (or decremented) 250after each transfer. In case of a ring buffer, they may loop 251(DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO) 252are typically fixed. 253 254Device operations 255----------------- 256 257Our dma_device structure also requires a few function pointers in 258order to implement the actual logic, now that we described what 259operations we were able to perform. 260 261The functions that we have to fill in there, and hence have to 262implement, obviously depend on the transaction types you reported as 263supported. 264 265- ``device_alloc_chan_resources`` 266 267- ``device_free_chan_resources`` 268 269 - These functions will be called whenever a driver will call 270 ``dma_request_channel`` or ``dma_release_channel`` for the first/last 271 time on the channel associated to that driver. 272 273 - They are in charge of allocating/freeing all the needed 274 resources in order for that channel to be useful for your driver. 275 276 - These functions can sleep. 277 278- ``device_prep_dma_*`` 279 280 - These functions are matching the capabilities you registered 281 previously. 282 283 - These functions all take the buffer or the scatterlist relevant 284 for the transfer being prepared, and should create a hardware 285 descriptor or a list of hardware descriptors from it 286 287 - These functions can be called from an interrupt context 288 289 - Any allocation you might do should be using the GFP_NOWAIT 290 flag, in order not to potentially sleep, but without depleting 291 the emergency pool either. 292 293 - Drivers should try to pre-allocate any memory they might need 294 during the transfer setup at probe time to avoid putting to 295 much pressure on the nowait allocator. 296 297 - It should return a unique instance of the 298 ``dma_async_tx_descriptor structure``, that further represents this 299 particular transfer. 300 301 - This structure can be initialized using the function 302 ``dma_async_tx_descriptor_init``. 303 304 - You'll also need to set two fields in this structure: 305 306 - flags: 307 TODO: Can it be modified by the driver itself, or 308 should it be always the flags passed in the arguments 309 310 - tx_submit: A pointer to a function you have to implement, 311 that is supposed to push the current transaction descriptor to a 312 pending queue, waiting for issue_pending to be called. 313 314 - In this structure the function pointer callback_result can be 315 initialized in order for the submitter to be notified that a 316 transaction has completed. In the earlier code the function pointer 317 callback has been used. However it does not provide any status to the 318 transaction and will be deprecated. The result structure defined as 319 ``dmaengine_result`` that is passed in to callback_result 320 has two fields: 321 322 - result: This provides the transfer result defined by 323 ``dmaengine_tx_result``. Either success or some error condition. 324 325 - residue: Provides the residue bytes of the transfer for those that 326 support residue. 327 328- ``device_issue_pending`` 329 330 - Takes the first transaction descriptor in the pending queue, 331 and starts the transfer. Whenever that transfer is done, it 332 should move to the next transaction in the list. 333 334 - This function can be called in an interrupt context 335 336- ``device_tx_status`` 337 338 - Should report the bytes left to go over on the given channel 339 340 - Should only care about the transaction descriptor passed as 341 argument, not the currently active one on a given channel 342 343 - The tx_state argument might be NULL 344 345 - Should use dma_set_residue to report it 346 347 - In the case of a cyclic transfer, it should only take into 348 account the current period. 349 350 - This function can be called in an interrupt context. 351 352- device_config 353 354 - Reconfigures the channel with the configuration given as argument 355 356 - This command should NOT perform synchronously, or on any 357 currently queued transfers, but only on subsequent ones 358 359 - In this case, the function will receive a ``dma_slave_config`` 360 structure pointer as an argument, that will detail which 361 configuration to use. 362 363 - Even though that structure contains a direction field, this 364 field is deprecated in favor of the direction argument given to 365 the prep_* functions 366 367 - This call is mandatory for slave operations only. This should NOT be 368 set or expected to be set for memcpy operations. 369 If a driver support both, it should use this call for slave 370 operations only and not for memcpy ones. 371 372- device_pause 373 374 - Pauses a transfer on the channel 375 376 - This command should operate synchronously on the channel, 377 pausing right away the work of the given channel 378 379- device_resume 380 381 - Resumes a transfer on the channel 382 383 - This command should operate synchronously on the channel, 384 resuming right away the work of the given channel 385 386- device_terminate_all 387 388 - Aborts all the pending and ongoing transfers on the channel 389 390 - For aborted transfers the complete callback should not be called 391 392 - Can be called from atomic context or from within a complete 393 callback of a descriptor. Must not sleep. Drivers must be able 394 to handle this correctly. 395 396 - Termination may be asynchronous. The driver does not have to 397 wait until the currently active transfer has completely stopped. 398 See device_synchronize. 399 400- device_synchronize 401 402 - Must synchronize the termination of a channel to the current 403 context. 404 405 - Must make sure that memory for previously submitted 406 descriptors is no longer accessed by the DMA controller. 407 408 - Must make sure that all complete callbacks for previously 409 submitted descriptors have finished running and none are 410 scheduled to run. 411 412 - May sleep. 413 414 415Misc notes 416========== 417 418(stuff that should be documented, but don't really know 419where to put them) 420 421``dma_run_dependencies`` 422 423- Should be called at the end of an async TX transfer, and can be 424 ignored in the slave transfers case. 425 426- Makes sure that dependent operations are run before marking it 427 as complete. 428 429dma_cookie_t 430 431- it's a DMA transaction ID that will increment over time. 432 433- Not really relevant any more since the introduction of ``virt-dma`` 434 that abstracts it away. 435 436DMA_CTRL_ACK 437 438- If clear, the descriptor cannot be reused by provider until the 439 client acknowledges receipt, i.e. has has a chance to establish any 440 dependency chains 441 442- This can be acked by invoking async_tx_ack() 443 444- If set, does not mean descriptor can be reused 445 446DMA_CTRL_REUSE 447 448- If set, the descriptor can be reused after being completed. It should 449 not be freed by provider if this flag is set. 450 451- The descriptor should be prepared for reuse by invoking 452 ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE. 453 454- ``dmaengine_desc_set_reuse()`` will succeed only when channel support 455 reusable descriptor as exhibited by capabilities 456 457- As a consequence, if a device driver wants to skip the 458 ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers, 459 because the DMA'd data wasn't used, it can resubmit the transfer right after 460 its completion. 461 462- Descriptor can be freed in few ways 463 464 - Clearing DMA_CTRL_REUSE by invoking 465 ``dmaengine_desc_clear_reuse()`` and submitting for last txn 466 467 - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only 468 when DMA_CTRL_REUSE is already set 469 470 - Terminating the channel 471 472- DMA_PREP_CMD 473 474 - If set, the client driver tells DMA controller that passed data in DMA 475 API is command data. 476 477 - Interpretation of command data is DMA controller specific. It can be 478 used for issuing commands to other peripherals/register reads/register 479 writes for which the descriptor should be in different format from 480 normal data descriptors. 481 482General Design Notes 483==================== 484 485Most of the DMAEngine drivers you'll see are based on a similar design 486that handles the end of transfer interrupts in the handler, but defer 487most work to a tasklet, including the start of a new transfer whenever 488the previous transfer ended. 489 490This is a rather inefficient design though, because the inter-transfer 491latency will be not only the interrupt latency, but also the 492scheduling latency of the tasklet, which will leave the channel idle 493in between, which will slow down the global transfer rate. 494 495You should avoid this kind of practice, and instead of electing a new 496transfer in your tasklet, move that part to the interrupt handler in 497order to have a shorter idle window (that we can't really avoid 498anyway). 499 500Glossary 501======== 502 503- Burst: A number of consecutive read or write operations that 504 can be queued to buffers before being flushed to memory. 505 506- Chunk: A contiguous collection of bursts 507 508- Transfer: A collection of chunks (be it contiguous or not) 509