1Buffer Sharing and Synchronization (dma-buf)
2============================================
3
4The dma-buf subsystem provides the framework for sharing buffers for
5hardware (DMA) access across multiple device drivers and subsystems, and
6for synchronizing asynchronous hardware access.
7
8This is used, for example, by drm "prime" multi-GPU support, but is of
9course not limited to GPU use cases.
10
11The three main components of this are: (1) dma-buf, representing a
12sg_table and exposed to userspace as a file descriptor to allow passing
13between devices, (2) fence, which provides a mechanism to signal when
14one device has finished access, and (3) reservation, which manages the
15shared or exclusive fence(s) associated with the buffer.
16
17Shared DMA Buffers
18------------------
19
20This document serves as a guide to device-driver writers on what is the dma-buf
21buffer sharing API, how to use it for exporting and using shared buffers.
22
23Any device driver which wishes to be a part of DMA buffer sharing, can do so as
24either the 'exporter' of buffers, or the 'user' or 'importer' of buffers.
25
26Say a driver A wants to use buffers created by driver B, then we call B as the
27exporter, and A as buffer-user/importer.
28
29The exporter
30
31 - implements and manages operations in :c:type:`struct dma_buf_ops
32   <dma_buf_ops>` for the buffer,
33 - allows other users to share the buffer by using dma_buf sharing APIs,
34 - manages the details of buffer allocation, wrapped in a :c:type:`struct
35   dma_buf <dma_buf>`,
36 - decides about the actual backing storage where this allocation happens,
37 - and takes care of any migration of scatterlist - for all (shared) users of
38   this buffer.
39
40The buffer-user
41
42 - is one of (many) sharing users of the buffer.
43 - doesn't need to worry about how the buffer is allocated, or where.
44 - and needs a mechanism to get access to the scatterlist that makes up this
45   buffer in memory, mapped into its own address space, so it can access the
46   same area of memory. This interface is provided by :c:type:`struct
47   dma_buf_attachment <dma_buf_attachment>`.
48
49Any exporters or users of the dma-buf buffer sharing framework must have a
50'select DMA_SHARED_BUFFER' in their respective Kconfigs.
51
52Userspace Interface Notes
53~~~~~~~~~~~~~~~~~~~~~~~~~
54
55Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
56and hence the generic interface exposed is very minimal. There's a few things to
57consider though:
58
59- Since kernel 3.12 the dma-buf FD supports the llseek system call, but only
60  with offset=0 and whence=SEEK_END|SEEK_SET. SEEK_SET is supported to allow
61  the usual size discover pattern size = SEEK_END(0); SEEK_SET(0). Every other
62  llseek operation will report -EINVAL.
63
64  If llseek on dma-buf FDs isn't support the kernel will report -ESPIPE for all
65  cases. Userspace can use this to detect support for discovering the dma-buf
66  size using llseek.
67
68- In order to avoid fd leaks on exec, the FD_CLOEXEC flag must be set
69  on the file descriptor.  This is not just a resource leak, but a
70  potential security hole.  It could give the newly exec'd application
71  access to buffers, via the leaked fd, to which it should otherwise
72  not be permitted access.
73
74  The problem with doing this via a separate fcntl() call, versus doing it
75  atomically when the fd is created, is that this is inherently racy in a
76  multi-threaded app[3].  The issue is made worse when it is library code
77  opening/creating the file descriptor, as the application may not even be
78  aware of the fd's.
79
80  To avoid this problem, userspace must have a way to request O_CLOEXEC
81  flag be set when the dma-buf fd is created.  So any API provided by
82  the exporting driver to create a dmabuf fd must provide a way to let
83  userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
84
85- Memory mapping the contents of the DMA buffer is also supported. See the
86  discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
87
88- The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
89  details.
90
91- The DMA buffer FD also supports a few dma-buf-specific ioctls, see
92  `DMA Buffer ioctls`_ below for details.
93
94Basic Operation and Device DMA Access
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
96
97.. kernel-doc:: drivers/dma-buf/dma-buf.c
98   :doc: dma buf device access
99
100CPU Access to DMA Buffer Objects
101~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
102
103.. kernel-doc:: drivers/dma-buf/dma-buf.c
104   :doc: cpu access
105
106Implicit Fence Poll Support
107~~~~~~~~~~~~~~~~~~~~~~~~~~~
108
109.. kernel-doc:: drivers/dma-buf/dma-buf.c
110   :doc: implicit fence polling
111
112DMA-BUF statistics
113~~~~~~~~~~~~~~~~~~
114.. kernel-doc:: drivers/dma-buf/dma-buf-sysfs-stats.c
115   :doc: overview
116
117DMA Buffer ioctls
118~~~~~~~~~~~~~~~~~
119
120.. kernel-doc:: include/uapi/linux/dma-buf.h
121
122DMA-BUF locking convention
123~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
124
125.. kernel-doc:: drivers/dma-buf/dma-buf.c
126   :doc: locking convention
127
128Kernel Functions and Structures Reference
129~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
130
131.. kernel-doc:: drivers/dma-buf/dma-buf.c
132   :export:
133
134.. kernel-doc:: include/linux/dma-buf.h
135   :internal:
136
137Reservation Objects
138-------------------
139
140.. kernel-doc:: drivers/dma-buf/dma-resv.c
141   :doc: Reservation Object Overview
142
143.. kernel-doc:: drivers/dma-buf/dma-resv.c
144   :export:
145
146.. kernel-doc:: include/linux/dma-resv.h
147   :internal:
148
149DMA Fences
150----------
151
152.. kernel-doc:: drivers/dma-buf/dma-fence.c
153   :doc: DMA fences overview
154
155DMA Fence Cross-Driver Contract
156~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
157
158.. kernel-doc:: drivers/dma-buf/dma-fence.c
159   :doc: fence cross-driver contract
160
161DMA Fence Signalling Annotations
162~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
163
164.. kernel-doc:: drivers/dma-buf/dma-fence.c
165   :doc: fence signalling annotation
166
167DMA Fences Functions Reference
168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
169
170.. kernel-doc:: drivers/dma-buf/dma-fence.c
171   :export:
172
173.. kernel-doc:: include/linux/dma-fence.h
174   :internal:
175
176DMA Fence Array
177~~~~~~~~~~~~~~~
178
179.. kernel-doc:: drivers/dma-buf/dma-fence-array.c
180   :export:
181
182.. kernel-doc:: include/linux/dma-fence-array.h
183   :internal:
184
185DMA Fence Chain
186~~~~~~~~~~~~~~~
187
188.. kernel-doc:: drivers/dma-buf/dma-fence-chain.c
189   :export:
190
191.. kernel-doc:: include/linux/dma-fence-chain.h
192   :internal:
193
194DMA Fence unwrap
195~~~~~~~~~~~~~~~~
196
197.. kernel-doc:: include/linux/dma-fence-unwrap.h
198   :internal:
199
200DMA Fence uABI/Sync File
201~~~~~~~~~~~~~~~~~~~~~~~~
202
203.. kernel-doc:: drivers/dma-buf/sync_file.c
204   :export:
205
206.. kernel-doc:: include/linux/sync_file.h
207   :internal:
208
209Indefinite DMA Fences
210~~~~~~~~~~~~~~~~~~~~~
211
212At various times struct dma_fence with an indefinite time until dma_fence_wait()
213finishes have been proposed. Examples include:
214
215* Future fences, used in HWC1 to signal when a buffer isn't used by the display
216  any longer, and created with the screen update that makes the buffer visible.
217  The time this fence completes is entirely under userspace's control.
218
219* Proxy fences, proposed to handle &drm_syncobj for which the fence has not yet
220  been set. Used to asynchronously delay command submission.
221
222* Userspace fences or gpu futexes, fine-grained locking within a command buffer
223  that userspace uses for synchronization across engines or with the CPU, which
224  are then imported as a DMA fence for integration into existing winsys
225  protocols.
226
227* Long-running compute command buffers, while still using traditional end of
228  batch DMA fences for memory management instead of context preemption DMA
229  fences which get reattached when the compute job is rescheduled.
230
231Common to all these schemes is that userspace controls the dependencies of these
232fences and controls when they fire. Mixing indefinite fences with normal
233in-kernel DMA fences does not work, even when a fallback timeout is included to
234protect against malicious userspace:
235
236* Only the kernel knows about all DMA fence dependencies, userspace is not aware
237  of dependencies injected due to memory management or scheduler decisions.
238
239* Only userspace knows about all dependencies in indefinite fences and when
240  exactly they will complete, the kernel has no visibility.
241
242Furthermore the kernel has to be able to hold up userspace command submission
243for memory management needs, which means we must support indefinite fences being
244dependent upon DMA fences. If the kernel also support indefinite fences in the
245kernel like a DMA fence, like any of the above proposal would, there is the
246potential for deadlocks.
247
248.. kernel-render:: DOT
249   :alt: Indefinite Fencing Dependency Cycle
250   :caption: Indefinite Fencing Dependency Cycle
251
252   digraph "Fencing Cycle" {
253      node [shape=box bgcolor=grey style=filled]
254      kernel [label="Kernel DMA Fences"]
255      userspace [label="userspace controlled fences"]
256      kernel -> userspace [label="memory management"]
257      userspace -> kernel [label="Future fence, fence proxy, ..."]
258
259      { rank=same; kernel userspace }
260   }
261
262This means that the kernel might accidentally create deadlocks
263through memory management dependencies which userspace is unaware of, which
264randomly hangs workloads until the timeout kicks in. Workloads, which from
265userspace's perspective, do not contain a deadlock.  In such a mixed fencing
266architecture there is no single entity with knowledge of all dependencies.
267Therefore preventing such deadlocks from within the kernel is not possible.
268
269The only solution to avoid dependencies loops is by not allowing indefinite
270fences in the kernel. This means:
271
272* No future fences, proxy fences or userspace fences imported as DMA fences,
273  with or without a timeout.
274
275* No DMA fences that signal end of batchbuffer for command submission where
276  userspace is allowed to use userspace fencing or long running compute
277  workloads. This also means no implicit fencing for shared buffers in these
278  cases.
279
280Recoverable Hardware Page Faults Implications
281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
282
283Modern hardware supports recoverable page faults, which has a lot of
284implications for DMA fences.
285
286First, a pending page fault obviously holds up the work that's running on the
287accelerator and a memory allocation is usually required to resolve the fault.
288But memory allocations are not allowed to gate completion of DMA fences, which
289means any workload using recoverable page faults cannot use DMA fences for
290synchronization. Synchronization fences controlled by userspace must be used
291instead.
292
293On GPUs this poses a problem, because current desktop compositor protocols on
294Linux rely on DMA fences, which means without an entirely new userspace stack
295built on top of userspace fences, they cannot benefit from recoverable page
296faults. Specifically this means implicit synchronization will not be possible.
297The exception is when page faults are only used as migration hints and never to
298on-demand fill a memory request. For now this means recoverable page
299faults on GPUs are limited to pure compute workloads.
300
301Furthermore GPUs usually have shared resources between the 3D rendering and
302compute side, like compute units or command submission engines. If both a 3D
303job with a DMA fence and a compute workload using recoverable page faults are
304pending they could deadlock:
305
306- The 3D workload might need to wait for the compute job to finish and release
307  hardware resources first.
308
309- The compute workload might be stuck in a page fault, because the memory
310  allocation is waiting for the DMA fence of the 3D workload to complete.
311
312There are a few options to prevent this problem, one of which drivers need to
313ensure:
314
315- Compute workloads can always be preempted, even when a page fault is pending
316  and not yet repaired. Not all hardware supports this.
317
318- DMA fence workloads and workloads which need page fault handling have
319  independent hardware resources to guarantee forward progress. This could be
320  achieved through e.g. through dedicated engines and minimal compute unit
321  reservations for DMA fence workloads.
322
323- The reservation approach could be further refined by only reserving the
324  hardware resources for DMA fence workloads when they are in-flight. This must
325  cover the time from when the DMA fence is visible to other threads up to
326  moment when fence is completed through dma_fence_signal().
327
328- As a last resort, if the hardware provides no useful reservation mechanics,
329  all workloads must be flushed from the GPU when switching between jobs
330  requiring DMA fences or jobs requiring page fault handling: This means all DMA
331  fences must complete before a compute job with page fault handling can be
332  inserted into the scheduler queue. And vice versa, before a DMA fence can be
333  made visible anywhere in the system, all compute workloads must be preempted
334  to guarantee all pending GPU page faults are flushed.
335
336- Only a fairly theoretical option would be to untangle these dependencies when
337  allocating memory to repair hardware page faults, either through separate
338  memory blocks or runtime tracking of the full dependency graph of all DMA
339  fences. This results very wide impact on the kernel, since resolving the page
340  on the CPU side can itself involve a page fault. It is much more feasible and
341  robust to limit the impact of handling hardware page faults to the specific
342  driver.
343
344Note that workloads that run on independent hardware like copy engines or other
345GPUs do not have any impact. This allows us to keep using DMA fences internally
346in the kernel even for resolving hardware page faults, e.g. by using copy
347engines to clear or copy memory needed to resolve the page fault.
348
349In some ways this page fault problem is a special case of the `Infinite DMA
350Fences` discussions: Infinite fences from compute workloads are allowed to
351depend on DMA fences, but not the other way around. And not even the page fault
352problem is new, because some other CPU thread in userspace might
353hit a page fault which holds up a userspace fence - supporting page faults on
354GPUs doesn't anything fundamentally new.
355