1df2634f4SSebastian Andrzej SiewiorCE4100 Device Tree Bindings 2df2634f4SSebastian Andrzej Siewior--------------------------- 3df2634f4SSebastian Andrzej Siewior 4df2634f4SSebastian Andrzej SiewiorThe CE4100 SoC uses for in core peripherals the following compatible 5df2634f4SSebastian Andrzej Siewiorformat: <vendor>,<chip>-<device>. 6df2634f4SSebastian Andrzej SiewiorMany of the "generic" devices like HPET or IO APIC have the ce4100 7df2634f4SSebastian Andrzej Siewiorname in their compatible property because they first appeared in this 8df2634f4SSebastian Andrzej SiewiorSoC. 9df2634f4SSebastian Andrzej Siewior 10df2634f4SSebastian Andrzej SiewiorThe CPU node 11df2634f4SSebastian Andrzej Siewior------------ 12df2634f4SSebastian Andrzej Siewior cpu@0 { 13df2634f4SSebastian Andrzej Siewior device_type = "cpu"; 14df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100"; 15df2634f4SSebastian Andrzej Siewior reg = <0>; 16df2634f4SSebastian Andrzej Siewior lapic = <&lapic0>; 17df2634f4SSebastian Andrzej Siewior }; 18df2634f4SSebastian Andrzej Siewior 19df2634f4SSebastian Andrzej SiewiorThe reg property describes the CPU number. The lapic property points to 20df2634f4SSebastian Andrzej Siewiorthe local APIC timer. 21df2634f4SSebastian Andrzej Siewior 22df2634f4SSebastian Andrzej SiewiorThe SoC node 23df2634f4SSebastian Andrzej Siewior------------ 24df2634f4SSebastian Andrzej Siewior 25df2634f4SSebastian Andrzej SiewiorThis node describes the in-core peripherals. Required property: 26df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100-cp"; 27df2634f4SSebastian Andrzej Siewior 28df2634f4SSebastian Andrzej SiewiorThe PCI node 29df2634f4SSebastian Andrzej Siewior------------ 30df2634f4SSebastian Andrzej SiewiorThis node describes the PCI bus on the SoC. Its property should be 31df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100-pci", "pci"; 32df2634f4SSebastian Andrzej Siewior 33df2634f4SSebastian Andrzej SiewiorIf the OS is using the IO-APIC for interrupt routing then the reported 34df2634f4SSebastian Andrzej Siewiorinterrupt numbers for devices is no longer true. In order to obtain the 35df2634f4SSebastian Andrzej Siewiorcorrect interrupt number, the child node which represents the device has 36df2634f4SSebastian Andrzej Siewiorto contain the interrupt property. Besides the interrupt property it has 37df2634f4SSebastian Andrzej Siewiorto contain at least the reg property containing the PCI bus address and 38df2634f4SSebastian Andrzej Siewiorcompatible property according to "PCI Bus Binding Revision 2.1". 39