1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,kpss-wdt-ipq4019
21              - qcom,apss-wdt-ipq5332
22              - qcom,apss-wdt-ipq9574
23              - qcom,apss-wdt-msm8994
24              - qcom,apss-wdt-qcm2290
25              - qcom,apss-wdt-qcs404
26              - qcom,apss-wdt-sa8775p
27              - qcom,apss-wdt-sc7180
28              - qcom,apss-wdt-sc7280
29              - qcom,apss-wdt-sc8180x
30              - qcom,apss-wdt-sc8280xp
31              - qcom,apss-wdt-sdm845
32              - qcom,apss-wdt-sdx55
33              - qcom,apss-wdt-sdx65
34              - qcom,apss-wdt-sm6350
35              - qcom,apss-wdt-sm8150
36              - qcom,apss-wdt-sm8250
37          - const: qcom,kpss-wdt
38      - const: qcom,kpss-wdt
39        deprecated: true
40      - items:
41          - const: qcom,scss-timer
42          - const: qcom,msm-timer
43      - items:
44          - enum:
45              - qcom,kpss-wdt-apq8064
46              - qcom,kpss-wdt-ipq8064
47              - qcom,kpss-wdt-mdm9615
48              - qcom,kpss-wdt-msm8960
49          - const: qcom,kpss-timer
50          - const: qcom,msm-timer
51
52  reg:
53    maxItems: 1
54
55  clocks:
56    maxItems: 1
57
58  clock-names:
59    items:
60      - const: sleep
61
62  clock-frequency:
63    description:
64      The frequency of the general purpose timer in Hz.
65
66  cpu-offset:
67    $ref: /schemas/types.yaml#/definitions/uint32
68    description:
69      Per-CPU offset used when the timer is accessed without the CPU remapping
70      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
71
72  interrupts:
73    minItems: 1
74    maxItems: 5
75
76required:
77  - compatible
78  - reg
79  - clocks
80
81allOf:
82  - $ref: watchdog.yaml#
83
84  - if:
85      properties:
86        compatible:
87          contains:
88            const: qcom,kpss-wdt
89    then:
90      properties:
91        clock-frequency: false
92        cpu-offset: false
93        interrupts:
94          minItems: 1
95          items:
96            - description: Bark
97            - description: Bite
98
99    else:
100      properties:
101        interrupts:
102          minItems: 3
103          items:
104            - description: Debug
105            - description: First general purpose timer
106            - description: Second general purpose timer
107            - description: First watchdog
108            - description: Second watchdog
109      required:
110        - clock-frequency
111
112unevaluatedProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/interrupt-controller/arm-gic.h>
117
118    watchdog@17c10000 {
119      compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
120      reg = <0x17c10000 0x1000>;
121      clocks = <&sleep_clk>;
122      interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
123      timeout-sec = <10>;
124    };
125
126  - |
127    #include <dt-bindings/interrupt-controller/arm-gic.h>
128
129    watchdog@200a000 {
130      compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
131      interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
132                   <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
133                   <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
134                   <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
135                   <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
136      reg = <0x0200a000 0x100>;
137      clock-frequency = <25000000>;
138      clocks = <&sleep_clk>;
139      clock-names = "sleep";
140      cpu-offset = <0x80000>;
141    };
142