1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/allwinner,sun4i-a10-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A10 Watchdog
8
9allOf:
10  - $ref: "watchdog.yaml#"
11
12maintainers:
13  - Chen-Yu Tsai <wens@csie.org>
14  - Maxime Ripard <mripard@kernel.org>
15
16properties:
17  compatible:
18    oneOf:
19      - const: allwinner,sun4i-a10-wdt
20      - const: allwinner,sun6i-a31-wdt
21      - items:
22          - enum:
23              - allwinner,sun50i-a64-wdt
24              - allwinner,sun50i-a100-wdt
25              - allwinner,sun50i-h6-wdt
26              - allwinner,sun50i-h616-wdt
27              - allwinner,sun50i-r329-wdt
28              - allwinner,sun50i-r329-wdt-reset
29              - allwinner,suniv-f1c100s-wdt
30          - const: allwinner,sun6i-a31-wdt
31      - const: allwinner,sun20i-d1-wdt
32      - items:
33          - const: allwinner,sun20i-d1-wdt-reset
34          - const: allwinner,sun20i-d1-wdt
35
36  reg:
37    maxItems: 1
38
39  clocks:
40    minItems: 1
41    items:
42      - description: 32 KHz input clock
43      - description: secondary clock source
44
45  interrupts:
46    maxItems: 1
47
48required:
49  - compatible
50  - reg
51  - clocks
52  - interrupts
53
54if:
55  properties:
56    compatible:
57      contains:
58        enum:
59          - allwinner,sun20i-d1-wdt
60          - allwinner,sun20i-d1-wdt-reset
61          - allwinner,sun50i-r329-wdt
62          - allwinner,sun50i-r329-wdt-reset
63
64then:
65  properties:
66    clocks:
67      items:
68        - description: High-frequency oscillator input, divided internally
69        - description: Low-frequency oscillator input
70
71    clock-names:
72      items:
73        - const: hosc
74        - const: losc
75
76  required:
77    - clock-names
78
79else:
80  properties:
81    clocks:
82      maxItems: 1
83
84unevaluatedProperties: false
85
86examples:
87  - |
88    wdt: watchdog@1c20c90 {
89        compatible = "allwinner,sun4i-a10-wdt";
90        reg = <0x01c20c90 0x10>;
91        interrupts = <24>;
92        clocks = <&osc24M>;
93        timeout-sec = <10>;
94    };
95
96...
97