1*803184f1SJean-Philippe Brucker# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*803184f1SJean-Philippe Brucker%YAML 1.2 3*803184f1SJean-Philippe Brucker--- 4*803184f1SJean-Philippe Brucker$id: http://devicetree.org/schemas/virtio/pci-iommu.yaml# 5*803184f1SJean-Philippe Brucker$schema: http://devicetree.org/meta-schemas/core.yaml# 6*803184f1SJean-Philippe Brucker 7*803184f1SJean-Philippe Bruckertitle: virtio-iommu device using the virtio-pci transport 8*803184f1SJean-Philippe Brucker 9*803184f1SJean-Philippe Bruckermaintainers: 10*803184f1SJean-Philippe Brucker - Jean-Philippe Brucker <jean-philippe@linaro.org> 11*803184f1SJean-Philippe Brucker 12*803184f1SJean-Philippe Bruckerdescription: | 13*803184f1SJean-Philippe Brucker When virtio-iommu uses the PCI transport, its programming interface is 14*803184f1SJean-Philippe Brucker discovered dynamically by the PCI probing infrastructure. However the 15*803184f1SJean-Philippe Brucker device tree statically describes the relation between IOMMU and DMA 16*803184f1SJean-Philippe Brucker masters. Therefore, the PCI root complex that hosts the virtio-iommu 17*803184f1SJean-Philippe Brucker contains a child node representing the IOMMU device explicitly. 18*803184f1SJean-Philippe Brucker 19*803184f1SJean-Philippe Brucker DMA from the IOMMU device isn't managed by another IOMMU. Therefore the 20*803184f1SJean-Philippe Brucker virtio-iommu node doesn't have an "iommus" property, and is omitted from 21*803184f1SJean-Philippe Brucker the iommu-map property of the root complex. 22*803184f1SJean-Philippe Brucker 23*803184f1SJean-Philippe Bruckerproperties: 24*803184f1SJean-Philippe Brucker # If compatible is present, it should contain the vendor and device ID 25*803184f1SJean-Philippe Brucker # according to the PCI Bus Binding specification. Since PCI provides 26*803184f1SJean-Philippe Brucker # built-in identification methods, compatible is not actually required. 27*803184f1SJean-Philippe Brucker compatible: 28*803184f1SJean-Philippe Brucker oneOf: 29*803184f1SJean-Philippe Brucker - items: 30*803184f1SJean-Philippe Brucker - const: virtio,pci-iommu 31*803184f1SJean-Philippe Brucker - const: pci1af4,1057 32*803184f1SJean-Philippe Brucker - items: 33*803184f1SJean-Philippe Brucker - const: pci1af4,1057 34*803184f1SJean-Philippe Brucker 35*803184f1SJean-Philippe Brucker reg: 36*803184f1SJean-Philippe Brucker description: | 37*803184f1SJean-Philippe Brucker PCI address of the IOMMU. As defined in the PCI Bus Binding 38*803184f1SJean-Philippe Brucker reference, the reg property is a five-cell address encoded as (phys.hi 39*803184f1SJean-Philippe Brucker phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's 40*803184f1SJean-Philippe Brucker BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be 41*803184f1SJean-Philippe Brucker zero. See Documentation/devicetree/bindings/pci/pci.txt 42*803184f1SJean-Philippe Brucker 43*803184f1SJean-Philippe Brucker '#iommu-cells': 44*803184f1SJean-Philippe Brucker const: 1 45*803184f1SJean-Philippe Brucker 46*803184f1SJean-Philippe Bruckerrequired: 47*803184f1SJean-Philippe Brucker - compatible 48*803184f1SJean-Philippe Brucker - reg 49*803184f1SJean-Philippe Brucker - '#iommu-cells' 50*803184f1SJean-Philippe Brucker 51*803184f1SJean-Philippe BruckeradditionalProperties: false 52*803184f1SJean-Philippe Brucker 53*803184f1SJean-Philippe Bruckerexamples: 54*803184f1SJean-Philippe Brucker - | 55*803184f1SJean-Philippe Brucker bus { 56*803184f1SJean-Philippe Brucker #address-cells = <2>; 57*803184f1SJean-Philippe Brucker #size-cells = <2>; 58*803184f1SJean-Philippe Brucker 59*803184f1SJean-Philippe Brucker pcie@40000000 { 60*803184f1SJean-Philippe Brucker device_type = "pci"; 61*803184f1SJean-Philippe Brucker #address-cells = <3>; 62*803184f1SJean-Philippe Brucker #size-cells = <2>; 63*803184f1SJean-Philippe Brucker reg = <0x0 0x40000000 0x0 0x1000000>; 64*803184f1SJean-Philippe Brucker ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>; 65*803184f1SJean-Philippe Brucker 66*803184f1SJean-Philippe Brucker /* 67*803184f1SJean-Philippe Brucker * The IOMMU manages all functions in this PCI domain except 68*803184f1SJean-Philippe Brucker * itself. Omit BDF 00:01.0. 69*803184f1SJean-Philippe Brucker */ 70*803184f1SJean-Philippe Brucker iommu-map = <0x0 &iommu0 0x0 0x8 71*803184f1SJean-Philippe Brucker 0x9 &iommu0 0x9 0xfff7>; 72*803184f1SJean-Philippe Brucker 73*803184f1SJean-Philippe Brucker /* The IOMMU programming interface uses slot 00:01.0 */ 74*803184f1SJean-Philippe Brucker iommu0: iommu@1,0 { 75*803184f1SJean-Philippe Brucker compatible = "pci1af4,1057"; 76*803184f1SJean-Philippe Brucker reg = <0x800 0 0 0 0>; 77*803184f1SJean-Philippe Brucker #iommu-cells = <1>; 78*803184f1SJean-Philippe Brucker }; 79*803184f1SJean-Philippe Brucker }; 80*803184f1SJean-Philippe Brucker 81*803184f1SJean-Philippe Brucker pcie@50000000 { 82*803184f1SJean-Philippe Brucker device_type = "pci"; 83*803184f1SJean-Philippe Brucker #address-cells = <3>; 84*803184f1SJean-Philippe Brucker #size-cells = <2>; 85*803184f1SJean-Philippe Brucker reg = <0x0 0x50000000 0x0 0x1000000>; 86*803184f1SJean-Philippe Brucker ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>; 87*803184f1SJean-Philippe Brucker 88*803184f1SJean-Philippe Brucker /* 89*803184f1SJean-Philippe Brucker * The IOMMU also manages all functions from this domain, 90*803184f1SJean-Philippe Brucker * with endpoint IDs 0x10000 - 0x1ffff 91*803184f1SJean-Philippe Brucker */ 92*803184f1SJean-Philippe Brucker iommu-map = <0x0 &iommu0 0x10000 0x10000>; 93*803184f1SJean-Philippe Brucker }; 94*803184f1SJean-Philippe Brucker 95*803184f1SJean-Philippe Brucker ethernet { 96*803184f1SJean-Philippe Brucker /* The IOMMU manages this platform device with endpoint ID 0x20000 */ 97*803184f1SJean-Philippe Brucker iommus = <&iommu0 0x20000>; 98*803184f1SJean-Philippe Brucker }; 99*803184f1SJean-Philippe Brucker }; 100*803184f1SJean-Philippe Brucker 101*803184f1SJean-Philippe Brucker... 102