1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
8
9maintainers:
10  - Roger Quadros <rogerq@ti.com>
11
12properties:
13  compatible:
14    oneOf:
15      - const: ti,j721e-usb
16      - const: ti,am64-usb
17      - items:
18          - const: ti,j721e-usb
19          - const: ti,am64-usb
20
21  reg:
22    description: module registers
23
24  ranges: true
25
26  power-domains:
27    description:
28      PM domain provider node and an args specifier containing
29      the USB device id value. See,
30      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
31
32  clocks:
33    description: Clock phandles to usb2_refclk and lpm_clk
34    minItems: 2
35    maxItems: 2
36
37  clock-names:
38    items:
39      - const: ref
40      - const: lpm
41
42  ti,usb2-only:
43    description:
44      If present, it restricts the controller to USB2.0 mode of
45      operation. Must be present if USB3 PHY is not available
46      for USB.
47    type: boolean
48
49  ti,vbus-divider:
50    description:
51      Should be present if USB VBUS line is connected to the
52      VBUS pin of the SoC via a 1/3 voltage divider.
53    type: boolean
54
55  assigned-clocks:
56    maxItems: 1
57
58  assigned-clock-parents:
59    maxItems: 1
60
61  '#address-cells':
62    const: 2
63
64  '#size-cells':
65    const: 2
66
67  dma-coherent: true
68
69patternProperties:
70  "^usb@":
71    type: object
72
73required:
74  - compatible
75  - reg
76  - power-domains
77  - clocks
78  - clock-names
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/soc/ti,sci_pm_domain.h>
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86
87    bus {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        cdns_usb@4104000 {
92            compatible = "ti,j721e-usb";
93            reg = <0x00 0x4104000 0x00 0x100>;
94            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
95            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
96            clock-names = "ref", "lpm";
97            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
98            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
99            #address-cells = <2>;
100            #size-cells = <2>;
101
102            usb@6000000 {
103                  compatible = "cdns,usb3";
104                  reg = <0x00 0x6000000 0x00 0x10000>,
105                        <0x00 0x6010000 0x00 0x10000>,
106                        <0x00 0x6020000 0x00 0x10000>;
107                  reg-names = "otg", "xhci", "dev";
108                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
109                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
110                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
111                  interrupt-names = "host",
112                                    "peripheral",
113                                    "otg";
114                  maximum-speed = "super-speed";
115                  dr_mode = "otg";
116            };
117        };
118    };
119