1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
8
9maintainers:
10  - Roger Quadros <rogerq@ti.com>
11
12properties:
13  compatible:
14    oneOf:
15      - const: ti,j721e-usb
16      - const: ti,am64-usb
17      - items:
18          - const: ti,j721e-usb
19          - const: ti,am64-usb
20
21  reg:
22    description: module registers
23
24  power-domains:
25    description:
26      PM domain provider node and an args specifier containing
27      the USB device id value. See,
28      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
29
30  clocks:
31    description: Clock phandles to usb2_refclk and lpm_clk
32    minItems: 2
33    maxItems: 2
34
35  clock-names:
36    items:
37      - const: ref
38      - const: lpm
39
40  ti,usb2-only:
41    description:
42      If present, it restricts the controller to USB2.0 mode of
43      operation. Must be present if USB3 PHY is not available
44      for USB.
45    type: boolean
46
47  ti,vbus-divider:
48    description:
49      Should be present if USB VBUS line is connected to the
50      VBUS pin of the SoC via a 1/3 voltage divider.
51    type: boolean
52
53  assigned-clocks:
54    maxItems: 1
55
56  assigned-clock-parents:
57    maxItems: 1
58
59  '#address-cells':
60    const: 2
61
62  '#size-cells':
63    const: 2
64
65patternProperties:
66  "^usb@":
67    type: object
68
69required:
70  - compatible
71  - reg
72  - power-domains
73  - clocks
74  - clock-names
75
76additionalProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/soc/ti,sci_pm_domain.h>
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82
83    bus {
84        #address-cells = <2>;
85        #size-cells = <2>;
86
87        cdns_usb@4104000 {
88            compatible = "ti,j721e-usb";
89            reg = <0x00 0x4104000 0x00 0x100>;
90            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
91            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
92            clock-names = "ref", "lpm";
93            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
94            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
95            #address-cells = <2>;
96            #size-cells = <2>;
97
98            usb@6000000 {
99                  compatible = "cdns,usb3";
100                  reg = <0x00 0x6000000 0x00 0x10000>,
101                        <0x00 0x6010000 0x00 0x10000>,
102                        <0x00 0x6020000 0x00 0x10000>;
103                  reg-names = "otg", "xhci", "dev";
104                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
105                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
106                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
107                  interrupt-names = "host",
108                                    "peripheral",
109                                    "otg";
110                  maximum-speed = "super-speed";
111                  dr_mode = "otg";
112            };
113        };
114    };
115