1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare USB3 Controller
8
9maintainers:
10  - Felipe Balbi <balbi@kernel.org>
11
12description:
13  This is usually a subnode to DWC3 glue to which it is connected, but can also
14  be presented as a standalone DT node with an optional vendor-specific
15  compatible string.
16
17allOf:
18  - $ref: usb-drd.yaml#
19  - if:
20      properties:
21        dr_mode:
22          const: peripheral
23
24      required:
25        - dr_mode
26    then:
27      $ref: usb.yaml#
28    else:
29      $ref: usb-xhci.yaml#
30
31properties:
32  compatible:
33    contains:
34      oneOf:
35        - const: snps,dwc3
36        - const: synopsys,dwc3
37          deprecated: true
38
39  interrupts:
40    description:
41      It's either a single common DWC3 interrupt (dwc_usb3) or individual
42      interrupts for the host, gadget and DRD modes.
43    minItems: 1
44    maxItems: 3
45
46  interrupt-names:
47    minItems: 1
48    maxItems: 3
49    oneOf:
50      - const: dwc_usb3
51      - items:
52          enum: [host, peripheral, otg]
53
54  clocks:
55    description:
56      In general the core supports three types of clocks. bus_early is a
57      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
58      PHY is suspended. suspend clocks a small part of the USB3 core when
59      SS PHY in P3. But particular cases may differ from that having less
60      or more clock sources with another names.
61
62  clock-names:
63    contains:
64      anyOf:
65        - enum: [bus_early, ref, suspend]
66        - true
67
68  usb-phy:
69    minItems: 1
70    items:
71      - description: USB2/HS PHY
72      - description: USB3/SS PHY
73
74  phys:
75    minItems: 1
76    maxItems: 2
77
78  phy-names:
79    minItems: 1
80    maxItems: 2
81    items:
82      enum:
83        - usb2-phy
84        - usb3-phy
85
86  resets:
87    minItems: 1
88
89  snps,usb2-lpm-disable:
90    description: Indicate if we don't want to enable USB2 HW LPM for host
91      mode.
92    type: boolean
93
94  snps,usb3_lpm_capable:
95    description: Determines if platform is USB3 LPM capable
96    type: boolean
97
98  snps,usb2-gadget-lpm-disable:
99    description: Indicate if we don't want to enable USB2 HW LPM for gadget
100      mode.
101    type: boolean
102
103  snps,dis-start-transfer-quirk:
104    description:
105      When set, disable isoc START TRANSFER command failure SW work-around
106      for DWC_usb31 version 1.70a-ea06 and prior.
107    type: boolean
108
109  snps,disable_scramble_quirk:
110    description:
111      True when SW should disable data scrambling. Only really useful for FPGA
112      builds.
113    type: boolean
114
115  snps,has-lpm-erratum:
116    description: True when DWC3 was configured with LPM Erratum enabled
117    type: boolean
118
119  snps,lpm-nyet-threshold:
120    description: LPM NYET threshold
121    $ref: /schemas/types.yaml#/definitions/uint8
122
123  snps,u2exit_lfps_quirk:
124    description: Set if we want to enable u2exit lfps quirk
125    type: boolean
126
127  snps,u2ss_inp3_quirk:
128    description: Set if we enable P3 OK for U2/SS Inactive quirk
129    type: boolean
130
131  snps,req_p1p2p3_quirk:
132    description:
133      When set, the core will always request for P1/P2/P3 transition sequence.
134    type: boolean
135
136  snps,del_p1p2p3_quirk:
137    description:
138      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
139      occur.
140    type: boolean
141
142  snps,del_phy_power_chg_quirk:
143    description: When set core will delay PHY power change from P0 to P1/P2/P3.
144    type: boolean
145
146  snps,lfps_filter_quirk:
147    description: When set core will filter LFPS reception.
148    type: boolean
149
150  snps,rx_detect_poll_quirk:
151    description:
152      when set core will disable a 400us delay to start Polling LFPS after
153      RX.Detect.
154    type: boolean
155
156  snps,tx_de_emphasis_quirk:
157    description: When set core will set Tx de-emphasis value
158    type: boolean
159
160  snps,tx_de_emphasis:
161    description:
162      The value driven to the PHY is controlled by the LTSSM during USB3
163      Compliance mode.
164    $ref: /schemas/types.yaml#/definitions/uint8
165    enum:
166      - 0 # -6dB de-emphasis
167      - 1 # -3.5dB de-emphasis
168      - 2 # No de-emphasis
169
170  snps,dis_u3_susphy_quirk:
171    description: When set core will disable USB3 suspend phy
172    type: boolean
173
174  snps,dis_u2_susphy_quirk:
175    description: When set core will disable USB2 suspend phy
176    type: boolean
177
178  snps,dis_enblslpm_quirk:
179    description:
180      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
181      to the PHY.
182    type: boolean
183
184  snps,dis-u1-entry-quirk:
185    description: Set if link entering into U1 needs to be disabled
186    type: boolean
187
188  snps,dis-u2-entry-quirk:
189    description: Set if link entering into U2 needs to be disabled
190    type: boolean
191
192  snps,dis_rxdet_inp3_quirk:
193    description:
194      When set core will disable receiver detection in PHY P3 power state.
195    type: boolean
196
197  snps,dis-u2-freeclk-exists-quirk:
198    description:
199      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
200      PHY doesn't provide a free-running PHY clock.
201    type: boolean
202
203  snps,dis-del-phy-power-chg-quirk:
204    description:
205      When set core will change PHY power from P0 to P1/P2/P3 without delay.
206    type: boolean
207
208  snps,dis-tx-ipgap-linecheck-quirk:
209    description: When set, disable u2mac linestate check during HS transmit
210    type: boolean
211
212  snps,parkmode-disable-ss-quirk:
213    description:
214      When set, all SuperSpeed bus instances in park mode are disabled.
215    type: boolean
216
217  snps,dis_metastability_quirk:
218    description:
219      When set, disable metastability workaround. CAUTION! Use only if you are
220      absolutely sure of it.
221    type: boolean
222
223  snps,dis-split-quirk:
224    description:
225      When set, change the way URBs are handled by the driver. Needed to
226      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
227    type: boolean
228
229  snps,is-utmi-l1-suspend:
230    description:
231      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
232      asserts utmi_sleep_n.
233    type: boolean
234
235  snps,hird-threshold:
236    description: HIRD threshold
237    $ref: /schemas/types.yaml#/definitions/uint8
238
239  snps,hsphy_interface:
240    description:
241      High-Speed PHY interface selection between UTMI+ and ULPI when the
242      DWC_USB3_HSPHY_INTERFACE has value 3.
243    $ref: /schemas/types.yaml#/definitions/uint8
244    enum: [utmi, ulpi]
245
246  snps,quirk-frame-length-adjustment:
247    description:
248      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
249      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
250      incorrect.
251    $ref: /schemas/types.yaml#/definitions/uint32
252    minimum: 0
253    maximum: 0x3f
254
255  snps,ref-clock-period-ns:
256    description:
257      Value for REFCLKPER field of GUCTL register for reference clock period in
258      nanoseconds, when the hardware set default does not match the actual
259      clock.
260    minimum: 1
261    maximum: 0x3ff
262
263  snps,rx-thr-num-pkt-prd:
264    description:
265      Periodic ESS RX packet threshold count (host mode only). Set this and
266      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
267      programming guide section 1.2.4) to enable periodic ESS RX threshold.
268    $ref: /schemas/types.yaml#/definitions/uint8
269    minimum: 1
270    maximum: 16
271
272  snps,rx-max-burst-prd:
273    description:
274      Max periodic ESS RX burst size (host mode only). Set this and
275      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
276      programming guide section 1.2.4) to enable periodic ESS RX threshold.
277    $ref: /schemas/types.yaml#/definitions/uint8
278    minimum: 1
279    maximum: 16
280
281  snps,tx-thr-num-pkt-prd:
282    description:
283      Periodic ESS TX packet threshold count (host mode only). Set this and
284      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
285      programming guide section 1.2.3) to enable periodic ESS TX threshold.
286    $ref: /schemas/types.yaml#/definitions/uint8
287    minimum: 1
288    maximum: 16
289
290  snps,tx-max-burst-prd:
291    description:
292      Max periodic ESS TX burst size (host mode only). Set this and
293      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
294      programming guide section 1.2.3) to enable periodic ESS TX threshold.
295    $ref: /schemas/types.yaml#/definitions/uint8
296    minimum: 1
297    maximum: 16
298
299  tx-fifo-resize:
300    description: Determines if the TX fifos can be dynamically resized depending
301      on the number of IN endpoints used and if bursting is supported.  This
302      may help improve bandwidth on platforms with higher system latencies, as
303      increased fifo space allows for the controller to prefetch data into its
304      internal memory.
305    type: boolean
306
307  tx-fifo-max-num:
308    description: Specifies the max number of packets the txfifo resizing logic
309      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
310      higher the number, the more fifo space the txfifo resizing logic will
311      allocate for that endpoint.
312    $ref: /schemas/types.yaml#/definitions/uint8
313    minimum: 3
314
315  snps,incr-burst-type-adjustment:
316    description:
317      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
318      burst type enable and INCRx type. A single value means INCRX burst mode
319      enabled. If more than one value specified, undefined length INCR burst
320      type will be enabled with burst lengths utilized up to the maximum
321      of the values passed in this property.
322    $ref: /schemas/types.yaml#/definitions/uint32-array
323    minItems: 1
324    maxItems: 8
325    uniqueItems: true
326    items:
327      enum: [1, 4, 8, 16, 32, 64, 128, 256]
328
329unevaluatedProperties: false
330
331required:
332  - compatible
333  - reg
334  - interrupts
335
336examples:
337  - |
338    usb@4a030000 {
339      compatible = "snps,dwc3";
340      reg = <0x4a030000 0xcfff>;
341      interrupts = <0 92 4>;
342      usb-phy = <&usb2_phy>, <&usb3_phy>;
343      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
344    };
345  - |
346    usb@4a000000 {
347      compatible = "snps,dwc3";
348      reg = <0x4a000000 0xcfff>;
349      interrupts = <0 92 4>;
350      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
351      clock-names = "bus_early", "ref", "suspend";
352      phys = <&usb2_phy>, <&usb3_phy>;
353      phy-names = "usb2-phy", "usb3-phy";
354      snps,dis_u2_susphy_quirk;
355      snps,dis_enblslpm_quirk;
356    };
357...
358