1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare USB3 Controller
8
9maintainers:
10  - Felipe Balbi <balbi@kernel.org>
11
12description:
13  This is usually a subnode to DWC3 glue to which it is connected, but can also
14  be presented as a standalone DT node with an optional vendor-specific
15  compatible string.
16
17allOf:
18  - $ref: usb-drd.yaml#
19  - if:
20      properties:
21        dr_mode:
22          const: peripheral
23
24      required:
25        - dr_mode
26    then:
27      $ref: usb.yaml#
28    else:
29      $ref: usb-xhci.yaml#
30
31properties:
32  compatible:
33    contains:
34      oneOf:
35        - const: snps,dwc3
36        - const: synopsys,dwc3
37          deprecated: true
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    description:
44      It's either a single common DWC3 interrupt (dwc_usb3) or individual
45      interrupts for the host, gadget and DRD modes.
46    minItems: 1
47    maxItems: 3
48
49  interrupt-names:
50    minItems: 1
51    maxItems: 3
52    oneOf:
53      - const: dwc_usb3
54      - items:
55          enum: [host, peripheral, otg]
56
57  clocks:
58    description:
59      In general the core supports three types of clocks. bus_early is a
60      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61      PHY is suspended. suspend clocks a small part of the USB3 core when
62      SS PHY in P3. But particular cases may differ from that having less
63      or more clock sources with another names.
64
65  clock-names:
66    contains:
67      anyOf:
68        - enum: [bus_early, ref, suspend]
69        - true
70
71  dma-coherent: true
72
73  iommus:
74    maxItems: 1
75
76  usb-phy:
77    minItems: 1
78    items:
79      - description: USB2/HS PHY
80      - description: USB3/SS PHY
81
82  phys:
83    minItems: 1
84    maxItems: 2
85
86  phy-names:
87    minItems: 1
88    maxItems: 2
89    items:
90      enum:
91        - usb2-phy
92        - usb3-phy
93
94  resets:
95    minItems: 1
96
97  snps,usb2-lpm-disable:
98    description: Indicate if we don't want to enable USB2 HW LPM for host
99      mode.
100    type: boolean
101
102  snps,usb3_lpm_capable:
103    description: Determines if platform is USB3 LPM capable
104    type: boolean
105
106  snps,usb2-gadget-lpm-disable:
107    description: Indicate if we don't want to enable USB2 HW LPM for gadget
108      mode.
109    type: boolean
110
111  snps,dis-start-transfer-quirk:
112    description:
113      When set, disable isoc START TRANSFER command failure SW work-around
114      for DWC_usb31 version 1.70a-ea06 and prior.
115    type: boolean
116
117  snps,disable_scramble_quirk:
118    description:
119      True when SW should disable data scrambling. Only really useful for FPGA
120      builds.
121    type: boolean
122
123  snps,has-lpm-erratum:
124    description: True when DWC3 was configured with LPM Erratum enabled
125    type: boolean
126
127  snps,lpm-nyet-threshold:
128    description: LPM NYET threshold
129    $ref: /schemas/types.yaml#/definitions/uint8
130
131  snps,u2exit_lfps_quirk:
132    description: Set if we want to enable u2exit lfps quirk
133    type: boolean
134
135  snps,u2ss_inp3_quirk:
136    description: Set if we enable P3 OK for U2/SS Inactive quirk
137    type: boolean
138
139  snps,req_p1p2p3_quirk:
140    description:
141      When set, the core will always request for P1/P2/P3 transition sequence.
142    type: boolean
143
144  snps,del_p1p2p3_quirk:
145    description:
146      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
147      occur.
148    type: boolean
149
150  snps,del_phy_power_chg_quirk:
151    description: When set core will delay PHY power change from P0 to P1/P2/P3.
152    type: boolean
153
154  snps,lfps_filter_quirk:
155    description: When set core will filter LFPS reception.
156    type: boolean
157
158  snps,rx_detect_poll_quirk:
159    description:
160      when set core will disable a 400us delay to start Polling LFPS after
161      RX.Detect.
162    type: boolean
163
164  snps,tx_de_emphasis_quirk:
165    description: When set core will set Tx de-emphasis value
166    type: boolean
167
168  snps,tx_de_emphasis:
169    description:
170      The value driven to the PHY is controlled by the LTSSM during USB3
171      Compliance mode.
172    $ref: /schemas/types.yaml#/definitions/uint8
173    enum:
174      - 0 # -6dB de-emphasis
175      - 1 # -3.5dB de-emphasis
176      - 2 # No de-emphasis
177
178  snps,dis_u3_susphy_quirk:
179    description: When set core will disable USB3 suspend phy
180    type: boolean
181
182  snps,dis_u2_susphy_quirk:
183    description: When set core will disable USB2 suspend phy
184    type: boolean
185
186  snps,dis_enblslpm_quirk:
187    description:
188      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
189      to the PHY.
190    type: boolean
191
192  snps,dis-u1-entry-quirk:
193    description: Set if link entering into U1 needs to be disabled
194    type: boolean
195
196  snps,dis-u2-entry-quirk:
197    description: Set if link entering into U2 needs to be disabled
198    type: boolean
199
200  snps,dis_rxdet_inp3_quirk:
201    description:
202      When set core will disable receiver detection in PHY P3 power state.
203    type: boolean
204
205  snps,dis-u2-freeclk-exists-quirk:
206    description:
207      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
208      PHY doesn't provide a free-running PHY clock.
209    type: boolean
210
211  snps,dis-del-phy-power-chg-quirk:
212    description:
213      When set core will change PHY power from P0 to P1/P2/P3 without delay.
214    type: boolean
215
216  snps,dis-tx-ipgap-linecheck-quirk:
217    description: When set, disable u2mac linestate check during HS transmit
218    type: boolean
219
220  snps,parkmode-disable-ss-quirk:
221    description:
222      When set, all SuperSpeed bus instances in park mode are disabled.
223    type: boolean
224
225  snps,dis_metastability_quirk:
226    description:
227      When set, disable metastability workaround. CAUTION! Use only if you are
228      absolutely sure of it.
229    type: boolean
230
231  snps,dis-split-quirk:
232    description:
233      When set, change the way URBs are handled by the driver. Needed to
234      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
235    type: boolean
236
237  snps,is-utmi-l1-suspend:
238    description:
239      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
240      asserts utmi_sleep_n.
241    type: boolean
242
243  snps,hird-threshold:
244    description: HIRD threshold
245    $ref: /schemas/types.yaml#/definitions/uint8
246
247  snps,hsphy_interface:
248    description:
249      High-Speed PHY interface selection between UTMI+ and ULPI when the
250      DWC_USB3_HSPHY_INTERFACE has value 3.
251    $ref: /schemas/types.yaml#/definitions/uint8
252    enum: [utmi, ulpi]
253
254  snps,quirk-frame-length-adjustment:
255    description:
256      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
257      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
258      incorrect.
259    $ref: /schemas/types.yaml#/definitions/uint32
260    minimum: 0
261    maximum: 0x3f
262
263  snps,ref-clock-period-ns:
264    description:
265      Value for REFCLKPER field of GUCTL register for reference clock period in
266      nanoseconds, when the hardware set default does not match the actual
267      clock.
268
269      This binding is deprecated. Instead, provide an appropriate reference clock.
270    minimum: 8
271    maximum: 62
272    deprecated: true
273
274  snps,rx-thr-num-pkt-prd:
275    description:
276      Periodic ESS RX packet threshold count (host mode only). Set this and
277      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
278      programming guide section 1.2.4) to enable periodic ESS RX threshold.
279    $ref: /schemas/types.yaml#/definitions/uint8
280    minimum: 1
281    maximum: 16
282
283  snps,rx-max-burst-prd:
284    description:
285      Max periodic ESS RX burst size (host mode only). Set this and
286      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
287      programming guide section 1.2.4) to enable periodic ESS RX threshold.
288    $ref: /schemas/types.yaml#/definitions/uint8
289    minimum: 1
290    maximum: 16
291
292  snps,tx-thr-num-pkt-prd:
293    description:
294      Periodic ESS TX packet threshold count (host mode only). Set this and
295      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
296      programming guide section 1.2.3) to enable periodic ESS TX threshold.
297    $ref: /schemas/types.yaml#/definitions/uint8
298    minimum: 1
299    maximum: 16
300
301  snps,tx-max-burst-prd:
302    description:
303      Max periodic ESS TX burst size (host mode only). Set this and
304      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
305      programming guide section 1.2.3) to enable periodic ESS TX threshold.
306    $ref: /schemas/types.yaml#/definitions/uint8
307    minimum: 1
308    maximum: 16
309
310  tx-fifo-resize:
311    description: Determines if the TX fifos can be dynamically resized depending
312      on the number of IN endpoints used and if bursting is supported.  This
313      may help improve bandwidth on platforms with higher system latencies, as
314      increased fifo space allows for the controller to prefetch data into its
315      internal memory.
316    type: boolean
317
318  tx-fifo-max-num:
319    description: Specifies the max number of packets the txfifo resizing logic
320      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
321      higher the number, the more fifo space the txfifo resizing logic will
322      allocate for that endpoint.
323    $ref: /schemas/types.yaml#/definitions/uint8
324    minimum: 3
325
326  snps,incr-burst-type-adjustment:
327    description:
328      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
329      burst type enable and INCRx type. A single value means INCRX burst mode
330      enabled. If more than one value specified, undefined length INCR burst
331      type will be enabled with burst lengths utilized up to the maximum
332      of the values passed in this property.
333    $ref: /schemas/types.yaml#/definitions/uint32-array
334    minItems: 1
335    maxItems: 8
336    uniqueItems: true
337    items:
338      enum: [1, 4, 8, 16, 32, 64, 128, 256]
339
340  port:
341    $ref: /schemas/graph.yaml#/properties/port
342    description:
343      This port is used with the 'usb-role-switch' property  to connect the
344      dwc3 to type C connector.
345
346unevaluatedProperties: false
347
348required:
349  - compatible
350  - reg
351  - interrupts
352
353examples:
354  - |
355    usb@4a030000 {
356      compatible = "snps,dwc3";
357      reg = <0x4a030000 0xcfff>;
358      interrupts = <0 92 4>;
359      usb-phy = <&usb2_phy>, <&usb3_phy>;
360      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
361    };
362  - |
363    usb@4a000000 {
364      compatible = "snps,dwc3";
365      reg = <0x4a000000 0xcfff>;
366      interrupts = <0 92 4>;
367      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
368      clock-names = "bus_early", "ref", "suspend";
369      phys = <&usb2_phy>, <&usb3_phy>;
370      phy-names = "usb2-phy", "usb3-phy";
371      snps,dis_u2_susphy_quirk;
372      snps,dis_enblslpm_quirk;
373    };
374...
375