1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare USB3 Controller
8
9maintainers:
10  - Felipe Balbi <balbi@kernel.org>
11
12description:
13  This is usually a subnode to DWC3 glue to which it is connected, but can also
14  be presented as a standalone DT node with an optional vendor-specific
15  compatible string.
16
17allOf:
18  - $ref: usb-drd.yaml#
19  - if:
20      properties:
21        dr_mode:
22          const: peripheral
23
24      required:
25        - dr_mode
26    then:
27      $ref: usb.yaml#
28    else:
29      $ref: usb-xhci.yaml#
30
31properties:
32  compatible:
33    contains:
34      oneOf:
35        - const: snps,dwc3
36        - const: synopsys,dwc3
37          deprecated: true
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    description:
44      It's either a single common DWC3 interrupt (dwc_usb3) or individual
45      interrupts for the host, gadget and DRD modes.
46    minItems: 1
47    maxItems: 3
48
49  interrupt-names:
50    minItems: 1
51    maxItems: 3
52    oneOf:
53      - const: dwc_usb3
54      - items:
55          enum: [host, peripheral, otg]
56
57  clocks:
58    description:
59      In general the core supports three types of clocks. bus_early is a
60      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61      PHY is suspended. suspend clocks a small part of the USB3 core when
62      SS PHY in P3. But particular cases may differ from that having less
63      or more clock sources with another names.
64
65  clock-names:
66    contains:
67      anyOf:
68        - enum: [bus_early, ref, suspend]
69        - true
70
71  iommus:
72    maxItems: 1
73
74  usb-phy:
75    minItems: 1
76    items:
77      - description: USB2/HS PHY
78      - description: USB3/SS PHY
79
80  phys:
81    minItems: 1
82    maxItems: 2
83
84  phy-names:
85    minItems: 1
86    maxItems: 2
87    items:
88      enum:
89        - usb2-phy
90        - usb3-phy
91
92  resets:
93    minItems: 1
94
95  snps,usb2-lpm-disable:
96    description: Indicate if we don't want to enable USB2 HW LPM for host
97      mode.
98    type: boolean
99
100  snps,usb3_lpm_capable:
101    description: Determines if platform is USB3 LPM capable
102    type: boolean
103
104  snps,usb2-gadget-lpm-disable:
105    description: Indicate if we don't want to enable USB2 HW LPM for gadget
106      mode.
107    type: boolean
108
109  snps,dis-start-transfer-quirk:
110    description:
111      When set, disable isoc START TRANSFER command failure SW work-around
112      for DWC_usb31 version 1.70a-ea06 and prior.
113    type: boolean
114
115  snps,disable_scramble_quirk:
116    description:
117      True when SW should disable data scrambling. Only really useful for FPGA
118      builds.
119    type: boolean
120
121  snps,has-lpm-erratum:
122    description: True when DWC3 was configured with LPM Erratum enabled
123    type: boolean
124
125  snps,lpm-nyet-threshold:
126    description: LPM NYET threshold
127    $ref: /schemas/types.yaml#/definitions/uint8
128
129  snps,u2exit_lfps_quirk:
130    description: Set if we want to enable u2exit lfps quirk
131    type: boolean
132
133  snps,u2ss_inp3_quirk:
134    description: Set if we enable P3 OK for U2/SS Inactive quirk
135    type: boolean
136
137  snps,req_p1p2p3_quirk:
138    description:
139      When set, the core will always request for P1/P2/P3 transition sequence.
140    type: boolean
141
142  snps,del_p1p2p3_quirk:
143    description:
144      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
145      occur.
146    type: boolean
147
148  snps,del_phy_power_chg_quirk:
149    description: When set core will delay PHY power change from P0 to P1/P2/P3.
150    type: boolean
151
152  snps,lfps_filter_quirk:
153    description: When set core will filter LFPS reception.
154    type: boolean
155
156  snps,rx_detect_poll_quirk:
157    description:
158      when set core will disable a 400us delay to start Polling LFPS after
159      RX.Detect.
160    type: boolean
161
162  snps,tx_de_emphasis_quirk:
163    description: When set core will set Tx de-emphasis value
164    type: boolean
165
166  snps,tx_de_emphasis:
167    description:
168      The value driven to the PHY is controlled by the LTSSM during USB3
169      Compliance mode.
170    $ref: /schemas/types.yaml#/definitions/uint8
171    enum:
172      - 0 # -6dB de-emphasis
173      - 1 # -3.5dB de-emphasis
174      - 2 # No de-emphasis
175
176  snps,dis_u3_susphy_quirk:
177    description: When set core will disable USB3 suspend phy
178    type: boolean
179
180  snps,dis_u2_susphy_quirk:
181    description: When set core will disable USB2 suspend phy
182    type: boolean
183
184  snps,dis_enblslpm_quirk:
185    description:
186      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
187      to the PHY.
188    type: boolean
189
190  snps,dis-u1-entry-quirk:
191    description: Set if link entering into U1 needs to be disabled
192    type: boolean
193
194  snps,dis-u2-entry-quirk:
195    description: Set if link entering into U2 needs to be disabled
196    type: boolean
197
198  snps,dis_rxdet_inp3_quirk:
199    description:
200      When set core will disable receiver detection in PHY P3 power state.
201    type: boolean
202
203  snps,dis-u2-freeclk-exists-quirk:
204    description:
205      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
206      PHY doesn't provide a free-running PHY clock.
207    type: boolean
208
209  snps,dis-del-phy-power-chg-quirk:
210    description:
211      When set core will change PHY power from P0 to P1/P2/P3 without delay.
212    type: boolean
213
214  snps,dis-tx-ipgap-linecheck-quirk:
215    description: When set, disable u2mac linestate check during HS transmit
216    type: boolean
217
218  snps,parkmode-disable-ss-quirk:
219    description:
220      When set, all SuperSpeed bus instances in park mode are disabled.
221    type: boolean
222
223  snps,dis_metastability_quirk:
224    description:
225      When set, disable metastability workaround. CAUTION! Use only if you are
226      absolutely sure of it.
227    type: boolean
228
229  snps,dis-split-quirk:
230    description:
231      When set, change the way URBs are handled by the driver. Needed to
232      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
233    type: boolean
234
235  snps,is-utmi-l1-suspend:
236    description:
237      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
238      asserts utmi_sleep_n.
239    type: boolean
240
241  snps,hird-threshold:
242    description: HIRD threshold
243    $ref: /schemas/types.yaml#/definitions/uint8
244
245  snps,hsphy_interface:
246    description:
247      High-Speed PHY interface selection between UTMI+ and ULPI when the
248      DWC_USB3_HSPHY_INTERFACE has value 3.
249    $ref: /schemas/types.yaml#/definitions/uint8
250    enum: [utmi, ulpi]
251
252  snps,quirk-frame-length-adjustment:
253    description:
254      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
255      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
256      incorrect.
257    $ref: /schemas/types.yaml#/definitions/uint32
258    minimum: 0
259    maximum: 0x3f
260
261  snps,ref-clock-period-ns:
262    description:
263      Value for REFCLKPER field of GUCTL register for reference clock period in
264      nanoseconds, when the hardware set default does not match the actual
265      clock.
266
267      This binding is deprecated. Instead, provide an appropriate reference clock.
268    minimum: 8
269    maximum: 62
270    deprecated: true
271
272  snps,rx-thr-num-pkt-prd:
273    description:
274      Periodic ESS RX packet threshold count (host mode only). Set this and
275      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
276      programming guide section 1.2.4) to enable periodic ESS RX threshold.
277    $ref: /schemas/types.yaml#/definitions/uint8
278    minimum: 1
279    maximum: 16
280
281  snps,rx-max-burst-prd:
282    description:
283      Max periodic ESS RX burst size (host mode only). Set this and
284      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
285      programming guide section 1.2.4) to enable periodic ESS RX threshold.
286    $ref: /schemas/types.yaml#/definitions/uint8
287    minimum: 1
288    maximum: 16
289
290  snps,tx-thr-num-pkt-prd:
291    description:
292      Periodic ESS TX packet threshold count (host mode only). Set this and
293      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
294      programming guide section 1.2.3) to enable periodic ESS TX threshold.
295    $ref: /schemas/types.yaml#/definitions/uint8
296    minimum: 1
297    maximum: 16
298
299  snps,tx-max-burst-prd:
300    description:
301      Max periodic ESS TX burst size (host mode only). Set this and
302      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
303      programming guide section 1.2.3) to enable periodic ESS TX threshold.
304    $ref: /schemas/types.yaml#/definitions/uint8
305    minimum: 1
306    maximum: 16
307
308  tx-fifo-resize:
309    description: Determines if the TX fifos can be dynamically resized depending
310      on the number of IN endpoints used and if bursting is supported.  This
311      may help improve bandwidth on platforms with higher system latencies, as
312      increased fifo space allows for the controller to prefetch data into its
313      internal memory.
314    type: boolean
315
316  tx-fifo-max-num:
317    description: Specifies the max number of packets the txfifo resizing logic
318      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
319      higher the number, the more fifo space the txfifo resizing logic will
320      allocate for that endpoint.
321    $ref: /schemas/types.yaml#/definitions/uint8
322    minimum: 3
323
324  snps,incr-burst-type-adjustment:
325    description:
326      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
327      burst type enable and INCRx type. A single value means INCRX burst mode
328      enabled. If more than one value specified, undefined length INCR burst
329      type will be enabled with burst lengths utilized up to the maximum
330      of the values passed in this property.
331    $ref: /schemas/types.yaml#/definitions/uint32-array
332    minItems: 1
333    maxItems: 8
334    uniqueItems: true
335    items:
336      enum: [1, 4, 8, 16, 32, 64, 128, 256]
337
338  port:
339    $ref: /schemas/graph.yaml#/properties/port
340    description:
341      This port is used with the 'usb-role-switch' property  to connect the
342      dwc3 to type C connector.
343
344unevaluatedProperties: false
345
346required:
347  - compatible
348  - reg
349  - interrupts
350
351examples:
352  - |
353    usb@4a030000 {
354      compatible = "snps,dwc3";
355      reg = <0x4a030000 0xcfff>;
356      interrupts = <0 92 4>;
357      usb-phy = <&usb2_phy>, <&usb3_phy>;
358      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
359    };
360  - |
361    usb@4a000000 {
362      compatible = "snps,dwc3";
363      reg = <0x4a000000 0xcfff>;
364      interrupts = <0 92 4>;
365      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
366      clock-names = "bus_early", "ref", "suspend";
367      phys = <&usb2_phy>, <&usb3_phy>;
368      phy-names = "usb2-phy", "usb3-phy";
369      snps,dis_u2_susphy_quirk;
370      snps,dis_enblslpm_quirk;
371    };
372...
373