1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare USB3 Controller
8
9maintainers:
10  - Felipe Balbi <balbi@kernel.org>
11
12description:
13  This is usually a subnode to DWC3 glue to which it is connected, but can also
14  be presented as a standalone DT node with an optional vendor-specific
15  compatible string.
16
17allOf:
18  - $ref: usb-drd.yaml#
19  - if:
20      properties:
21        dr_mode:
22          const: peripheral
23
24      required:
25        - dr_mode
26    then:
27      $ref: usb.yaml#
28    else:
29      $ref: usb-xhci.yaml#
30
31properties:
32  compatible:
33    contains:
34      oneOf:
35        - const: snps,dwc3
36        - const: synopsys,dwc3
37          deprecated: true
38
39  reg:
40    maxItems: 1
41
42  interrupts:
43    description:
44      It's either a single common DWC3 interrupt (dwc_usb3) or individual
45      interrupts for the host, gadget and DRD modes.
46    minItems: 1
47    maxItems: 3
48
49  interrupt-names:
50    minItems: 1
51    maxItems: 3
52    oneOf:
53      - const: dwc_usb3
54      - items:
55          enum: [host, peripheral, otg]
56
57  clocks:
58    description:
59      In general the core supports three types of clocks. bus_early is a
60      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61      PHY is suspended. suspend clocks a small part of the USB3 core when
62      SS PHY in P3. But particular cases may differ from that having less
63      or more clock sources with another names.
64
65  clock-names:
66    contains:
67      anyOf:
68        - enum: [bus_early, ref, suspend]
69        - true
70
71  dma-coherent: true
72
73  iommus:
74    maxItems: 1
75
76  usb-phy:
77    minItems: 1
78    items:
79      - description: USB2/HS PHY
80      - description: USB3/SS PHY
81
82  phys:
83    minItems: 1
84    maxItems: 2
85
86  phy-names:
87    minItems: 1
88    maxItems: 2
89    items:
90      enum:
91        - usb2-phy
92        - usb3-phy
93
94  power-domains:
95    description:
96      The DWC3 has 2 power-domains. The power management unit (PMU) and
97      everything else. The PMU is typically always powered and may not have an
98      entry.
99    minItems: 1
100    items:
101      - description: Core
102      - description: Power management unit
103
104  resets:
105    minItems: 1
106
107  snps,usb2-lpm-disable:
108    description: Indicate if we don't want to enable USB2 HW LPM for host
109      mode.
110    type: boolean
111
112  snps,usb3_lpm_capable:
113    description: Determines if platform is USB3 LPM capable
114    type: boolean
115
116  snps,usb2-gadget-lpm-disable:
117    description: Indicate if we don't want to enable USB2 HW LPM for gadget
118      mode.
119    type: boolean
120
121  snps,dis-start-transfer-quirk:
122    description:
123      When set, disable isoc START TRANSFER command failure SW work-around
124      for DWC_usb31 version 1.70a-ea06 and prior.
125    type: boolean
126
127  snps,disable_scramble_quirk:
128    description:
129      True when SW should disable data scrambling. Only really useful for FPGA
130      builds.
131    type: boolean
132
133  snps,has-lpm-erratum:
134    description: True when DWC3 was configured with LPM Erratum enabled
135    type: boolean
136
137  snps,lpm-nyet-threshold:
138    description: LPM NYET threshold
139    $ref: /schemas/types.yaml#/definitions/uint8
140
141  snps,u2exit_lfps_quirk:
142    description: Set if we want to enable u2exit lfps quirk
143    type: boolean
144
145  snps,u2ss_inp3_quirk:
146    description: Set if we enable P3 OK for U2/SS Inactive quirk
147    type: boolean
148
149  snps,req_p1p2p3_quirk:
150    description:
151      When set, the core will always request for P1/P2/P3 transition sequence.
152    type: boolean
153
154  snps,del_p1p2p3_quirk:
155    description:
156      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
157      occur.
158    type: boolean
159
160  snps,del_phy_power_chg_quirk:
161    description: When set core will delay PHY power change from P0 to P1/P2/P3.
162    type: boolean
163
164  snps,lfps_filter_quirk:
165    description: When set core will filter LFPS reception.
166    type: boolean
167
168  snps,rx_detect_poll_quirk:
169    description:
170      when set core will disable a 400us delay to start Polling LFPS after
171      RX.Detect.
172    type: boolean
173
174  snps,tx_de_emphasis_quirk:
175    description: When set core will set Tx de-emphasis value
176    type: boolean
177
178  snps,tx_de_emphasis:
179    description:
180      The value driven to the PHY is controlled by the LTSSM during USB3
181      Compliance mode.
182    $ref: /schemas/types.yaml#/definitions/uint8
183    enum:
184      - 0 # -6dB de-emphasis
185      - 1 # -3.5dB de-emphasis
186      - 2 # No de-emphasis
187
188  snps,dis_u3_susphy_quirk:
189    description: When set core will disable USB3 suspend phy
190    type: boolean
191
192  snps,dis_u2_susphy_quirk:
193    description: When set core will disable USB2 suspend phy
194    type: boolean
195
196  snps,dis_enblslpm_quirk:
197    description:
198      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
199      to the PHY.
200    type: boolean
201
202  snps,dis-u1-entry-quirk:
203    description: Set if link entering into U1 needs to be disabled
204    type: boolean
205
206  snps,dis-u2-entry-quirk:
207    description: Set if link entering into U2 needs to be disabled
208    type: boolean
209
210  snps,dis_rxdet_inp3_quirk:
211    description:
212      When set core will disable receiver detection in PHY P3 power state.
213    type: boolean
214
215  snps,dis-u2-freeclk-exists-quirk:
216    description:
217      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
218      PHY doesn't provide a free-running PHY clock.
219    type: boolean
220
221  snps,dis-del-phy-power-chg-quirk:
222    description:
223      When set core will change PHY power from P0 to P1/P2/P3 without delay.
224    type: boolean
225
226  snps,dis-tx-ipgap-linecheck-quirk:
227    description: When set, disable u2mac linestate check during HS transmit
228    type: boolean
229
230  snps,parkmode-disable-ss-quirk:
231    description:
232      When set, all SuperSpeed bus instances in park mode are disabled.
233    type: boolean
234
235  snps,dis_metastability_quirk:
236    description:
237      When set, disable metastability workaround. CAUTION! Use only if you are
238      absolutely sure of it.
239    type: boolean
240
241  snps,dis-split-quirk:
242    description:
243      When set, change the way URBs are handled by the driver. Needed to
244      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
245    type: boolean
246
247  snps,gfladj-refclk-lpm-sel-quirk:
248    description:
249      When set, run the SOF/ITP counter based on ref_clk.
250    type: boolean
251
252  snps,resume-hs-terminations:
253    description:
254      Fix the issue of HS terminations CRC error on resume by enabling this
255      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
256      of resume. This option is to support certain legacy ULPI PHYs.
257    type: boolean
258
259  snps,is-utmi-l1-suspend:
260    description:
261      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
262      asserts utmi_sleep_n.
263    type: boolean
264
265  snps,hird-threshold:
266    description: HIRD threshold
267    $ref: /schemas/types.yaml#/definitions/uint8
268
269  snps,hsphy_interface:
270    description:
271      High-Speed PHY interface selection between UTMI+ and ULPI when the
272      DWC_USB3_HSPHY_INTERFACE has value 3.
273    $ref: /schemas/types.yaml#/definitions/uint8
274    enum: [utmi, ulpi]
275
276  snps,quirk-frame-length-adjustment:
277    description:
278      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
279      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
280      incorrect.
281    $ref: /schemas/types.yaml#/definitions/uint32
282    minimum: 0
283    maximum: 0x3f
284
285  snps,ref-clock-period-ns:
286    description:
287      Value for REFCLKPER field of GUCTL register for reference clock period in
288      nanoseconds, when the hardware set default does not match the actual
289      clock.
290
291      This binding is deprecated. Instead, provide an appropriate reference clock.
292    minimum: 8
293    maximum: 62
294    deprecated: true
295
296  snps,rx-thr-num-pkt-prd:
297    description:
298      Periodic ESS RX packet threshold count (host mode only). Set this and
299      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
300      programming guide section 1.2.4) to enable periodic ESS RX threshold.
301    $ref: /schemas/types.yaml#/definitions/uint8
302    minimum: 1
303    maximum: 16
304
305  snps,rx-max-burst-prd:
306    description:
307      Max periodic ESS RX burst size (host mode only). Set this and
308      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
309      programming guide section 1.2.4) to enable periodic ESS RX threshold.
310    $ref: /schemas/types.yaml#/definitions/uint8
311    minimum: 1
312    maximum: 16
313
314  snps,tx-thr-num-pkt-prd:
315    description:
316      Periodic ESS TX packet threshold count (host mode only). Set this and
317      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
318      programming guide section 1.2.3) to enable periodic ESS TX threshold.
319    $ref: /schemas/types.yaml#/definitions/uint8
320    minimum: 1
321    maximum: 16
322
323  snps,tx-max-burst-prd:
324    description:
325      Max periodic ESS TX burst size (host mode only). Set this and
326      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
327      programming guide section 1.2.3) to enable periodic ESS TX threshold.
328    $ref: /schemas/types.yaml#/definitions/uint8
329    minimum: 1
330    maximum: 16
331
332  tx-fifo-resize:
333    description: Determines if the TX fifos can be dynamically resized depending
334      on the number of IN endpoints used and if bursting is supported.  This
335      may help improve bandwidth on platforms with higher system latencies, as
336      increased fifo space allows for the controller to prefetch data into its
337      internal memory.
338    type: boolean
339
340  tx-fifo-max-num:
341    description: Specifies the max number of packets the txfifo resizing logic
342      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
343      higher the number, the more fifo space the txfifo resizing logic will
344      allocate for that endpoint.
345    $ref: /schemas/types.yaml#/definitions/uint8
346    minimum: 3
347
348  snps,incr-burst-type-adjustment:
349    description:
350      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
351      burst type enable and INCRx type. A single value means INCRX burst mode
352      enabled. If more than one value specified, undefined length INCR burst
353      type will be enabled with burst lengths utilized up to the maximum
354      of the values passed in this property.
355    $ref: /schemas/types.yaml#/definitions/uint32-array
356    minItems: 1
357    maxItems: 8
358    uniqueItems: true
359    items:
360      enum: [1, 4, 8, 16, 32, 64, 128, 256]
361
362  port:
363    $ref: /schemas/graph.yaml#/properties/port
364    description:
365      This port is used with the 'usb-role-switch' property  to connect the
366      dwc3 to type C connector.
367
368  wakeup-source:
369    $ref: /schemas/types.yaml#/definitions/flag
370    description:
371      Enable USB remote wakeup.
372
373unevaluatedProperties: false
374
375required:
376  - compatible
377  - reg
378  - interrupts
379
380examples:
381  - |
382    usb@4a030000 {
383      compatible = "snps,dwc3";
384      reg = <0x4a030000 0xcfff>;
385      interrupts = <0 92 4>;
386      usb-phy = <&usb2_phy>, <&usb3_phy>;
387      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
388    };
389  - |
390    usb@4a000000 {
391      compatible = "snps,dwc3";
392      reg = <0x4a000000 0xcfff>;
393      interrupts = <0 92 4>;
394      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
395      clock-names = "bus_early", "ref", "suspend";
396      phys = <&usb2_phy>, <&usb3_phy>;
397      phy-names = "usb2-phy", "usb3-phy";
398      snps,dis_u2_susphy_quirk;
399      snps,dis_enblslpm_quirk;
400    };
401...
402