1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Wesley Cheng <quic_wcheng@quicinc.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq4019-dwc3
17          - qcom,ipq6018-dwc3
18          - qcom,ipq8064-dwc3
19          - qcom,ipq8074-dwc3
20          - qcom,msm8953-dwc3
21          - qcom,msm8994-dwc3
22          - qcom,msm8996-dwc3
23          - qcom,msm8998-dwc3
24          - qcom,qcm2290-dwc3
25          - qcom,qcs404-dwc3
26          - qcom,sc7180-dwc3
27          - qcom,sc7280-dwc3
28          - qcom,sc8280xp-dwc3
29          - qcom,sdm660-dwc3
30          - qcom,sdm670-dwc3
31          - qcom,sdm845-dwc3
32          - qcom,sdx55-dwc3
33          - qcom,sdx65-dwc3
34          - qcom,sm4250-dwc3
35          - qcom,sm6115-dwc3
36          - qcom,sm6125-dwc3
37          - qcom,sm6350-dwc3
38          - qcom,sm6375-dwc3
39          - qcom,sm8150-dwc3
40          - qcom,sm8250-dwc3
41          - qcom,sm8350-dwc3
42          - qcom,sm8450-dwc3
43          - qcom,sm8550-dwc3
44      - const: qcom,dwc3
45
46  reg:
47    description: Offset and length of register set for QSCRATCH wrapper
48    maxItems: 1
49
50  "#address-cells":
51    enum: [ 1, 2 ]
52
53  "#size-cells":
54    enum: [ 1, 2 ]
55
56  ranges: true
57
58  power-domains:
59    description: specifies a phandle to PM domain provider node
60    maxItems: 1
61
62  required-opps:
63    maxItems: 1
64
65  clocks:
66    description: |
67      Several clocks are used, depending on the variant. Typical ones are::
68       - cfg_noc:: System Config NOC clock.
69       - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
70                60MHz for HS operation.
71       - iface:: System bus AXI clock.
72       - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
73                 power mode (U3).
74       - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
75                     mode. Its frequency should be 19.2MHz.
76    minItems: 1
77    maxItems: 9
78
79  clock-names:
80    minItems: 1
81    maxItems: 9
82
83  assigned-clocks:
84    items:
85      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
86      - description: Phandle and clock specifoer of MASTER_CLK.
87
88  assigned-clock-rates:
89    items:
90      - description: Must be 19.2MHz (19200000).
91      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
92  resets:
93    maxItems: 1
94
95  interconnects:
96    maxItems: 2
97
98  interconnect-names:
99    items:
100      - const: usb-ddr
101      - const: apps-usb
102
103  interrupts:
104    minItems: 1
105    maxItems: 4
106
107  interrupt-names:
108    minItems: 1
109    maxItems: 4
110
111  qcom,select-utmi-as-pipe-clk:
112    description:
113      If present, disable USB3 pipe_clk requirement.
114      Used when dwc3 operates without SSPHY and only
115      HS/FS/LS modes are supported.
116    type: boolean
117
118  wakeup-source: true
119
120# Required child node:
121
122patternProperties:
123  "^usb@[0-9a-f]+$":
124    $ref: snps,dwc3.yaml#
125    unevaluatedProperties: false
126
127    properties:
128      wakeup-source: false
129
130required:
131  - compatible
132  - reg
133  - "#address-cells"
134  - "#size-cells"
135  - ranges
136  - power-domains
137  - clocks
138  - clock-names
139  - interrupts
140  - interrupt-names
141
142allOf:
143  - if:
144      properties:
145        compatible:
146          contains:
147            enum:
148              - qcom,ipq4019-dwc3
149    then:
150      properties:
151        clocks:
152          maxItems: 3
153        clock-names:
154          items:
155            - const: core
156            - const: sleep
157            - const: mock_utmi
158
159  - if:
160      properties:
161        compatible:
162          contains:
163            enum:
164              - qcom,ipq8064-dwc3
165    then:
166      properties:
167        clocks:
168          items:
169            - description: Master/Core clock, has to be >= 125 MHz
170                for SS operation and >= 60MHz for HS operation.
171        clock-names:
172          items:
173            - const: core
174
175  - if:
176      properties:
177        compatible:
178          contains:
179            enum:
180              - qcom,msm8953-dwc3
181              - qcom,msm8996-dwc3
182              - qcom,msm8998-dwc3
183              - qcom,sc7180-dwc3
184              - qcom,sc7280-dwc3
185              - qcom,sdm670-dwc3
186              - qcom,sdm845-dwc3
187              - qcom,sdx55-dwc3
188              - qcom,sm6350-dwc3
189    then:
190      properties:
191        clocks:
192          maxItems: 5
193        clock-names:
194          items:
195            - const: cfg_noc
196            - const: core
197            - const: iface
198            - const: sleep
199            - const: mock_utmi
200
201  - if:
202      properties:
203        compatible:
204          contains:
205            enum:
206              - qcom,ipq6018-dwc3
207    then:
208      properties:
209        clocks:
210          minItems: 3
211          maxItems: 4
212        clock-names:
213          oneOf:
214            - items:
215                - const: core
216                - const: sleep
217                - const: mock_utmi
218            - items:
219                - const: cfg_noc
220                - const: core
221                - const: sleep
222                - const: mock_utmi
223
224  - if:
225      properties:
226        compatible:
227          contains:
228            enum:
229              - qcom,ipq8074-dwc3
230    then:
231      properties:
232        clocks:
233          maxItems: 4
234        clock-names:
235          items:
236            - const: cfg_noc
237            - const: core
238            - const: sleep
239            - const: mock_utmi
240
241  - if:
242      properties:
243        compatible:
244          contains:
245            enum:
246              - qcom,msm8994-dwc3
247              - qcom,qcs404-dwc3
248    then:
249      properties:
250        clocks:
251          maxItems: 4
252        clock-names:
253          items:
254            - const: core
255            - const: iface
256            - const: sleep
257            - const: mock_utmi
258
259  - if:
260      properties:
261        compatible:
262          contains:
263            enum:
264              - qcom,sc8280xp-dwc3
265    then:
266      properties:
267        clocks:
268          maxItems: 9
269        clock-names:
270          items:
271            - const: cfg_noc
272            - const: core
273            - const: iface
274            - const: sleep
275            - const: mock_utmi
276            - const: noc_aggr
277            - const: noc_aggr_north
278            - const: noc_aggr_south
279            - const: noc_sys
280
281  - if:
282      properties:
283        compatible:
284          contains:
285            enum:
286              - qcom,sdm660-dwc3
287    then:
288      properties:
289        clocks:
290          minItems: 6
291        clock-names:
292          items:
293            - const: cfg_noc
294            - const: core
295            - const: iface
296            - const: sleep
297            - const: mock_utmi
298            - const: bus
299
300  - if:
301      properties:
302        compatible:
303          contains:
304            enum:
305              - qcom,qcm2290-dwc3
306              - qcom,sm6115-dwc3
307              - qcom,sm6125-dwc3
308              - qcom,sm8150-dwc3
309              - qcom,sm8250-dwc3
310              - qcom,sm8450-dwc3
311              - qcom,sm8550-dwc3
312    then:
313      properties:
314        clocks:
315          minItems: 6
316        clock-names:
317          items:
318            - const: cfg_noc
319            - const: core
320            - const: iface
321            - const: sleep
322            - const: mock_utmi
323            - const: xo
324
325  - if:
326      properties:
327        compatible:
328          contains:
329            enum:
330              - qcom,sm8350-dwc3
331    then:
332      properties:
333        clocks:
334          minItems: 5
335          maxItems: 6
336        clock-names:
337          minItems: 5
338          items:
339            - const: cfg_noc
340            - const: core
341            - const: iface
342            - const: sleep
343            - const: mock_utmi
344            - const: xo
345
346  - if:
347      properties:
348        compatible:
349          contains:
350            enum:
351              - qcom,ipq4019-dwc3
352              - qcom,ipq6018-dwc3
353              - qcom,ipq8064-dwc3
354              - qcom,ipq8074-dwc3
355              - qcom,msm8994-dwc3
356              - qcom,qcs404-dwc3
357              - qcom,sc7180-dwc3
358              - qcom,sdm670-dwc3
359              - qcom,sdm845-dwc3
360              - qcom,sdx55-dwc3
361              - qcom,sdx65-dwc3
362              - qcom,sm4250-dwc3
363              - qcom,sm6125-dwc3
364              - qcom,sm6350-dwc3
365              - qcom,sm8150-dwc3
366              - qcom,sm8250-dwc3
367              - qcom,sm8350-dwc3
368              - qcom,sm8450-dwc3
369              - qcom,sm8550-dwc3
370    then:
371      properties:
372        interrupts:
373          items:
374            - description: The interrupt that is asserted
375                when a wakeup event is received on USB2 bus.
376            - description: The interrupt that is asserted
377                when a wakeup event is received on USB3 bus.
378            - description: Wakeup event on DM line.
379            - description: Wakeup event on DP line.
380        interrupt-names:
381          items:
382            - const: hs_phy_irq
383            - const: ss_phy_irq
384            - const: dm_hs_phy_irq
385            - const: dp_hs_phy_irq
386
387  - if:
388      properties:
389        compatible:
390          contains:
391            enum:
392              - qcom,msm8953-dwc3
393              - qcom,msm8996-dwc3
394              - qcom,msm8998-dwc3
395              - qcom,sm6115-dwc3
396    then:
397      properties:
398        interrupts:
399          maxItems: 2
400        interrupt-names:
401          items:
402            - const: hs_phy_irq
403            - const: ss_phy_irq
404
405  - if:
406      properties:
407        compatible:
408          contains:
409            enum:
410              - qcom,sdm660-dwc3
411    then:
412      properties:
413        interrupts:
414          minItems: 1
415          maxItems: 2
416        interrupt-names:
417          minItems: 1
418          items:
419            - const: hs_phy_irq
420            - const: ss_phy_irq
421
422  - if:
423      properties:
424        compatible:
425          contains:
426            enum:
427              - qcom,sc7280-dwc3
428    then:
429      properties:
430        interrupts:
431          minItems: 3
432          maxItems: 4
433        interrupt-names:
434          minItems: 3
435          items:
436            - const: hs_phy_irq
437            - const: dp_hs_phy_irq
438            - const: dm_hs_phy_irq
439            - const: ss_phy_irq
440
441  - if:
442      properties:
443        compatible:
444          contains:
445            enum:
446              - qcom,sc8280xp-dwc3
447    then:
448      properties:
449        interrupts:
450          maxItems: 4
451        interrupt-names:
452          items:
453            - const: pwr_event
454            - const: dp_hs_phy_irq
455            - const: dm_hs_phy_irq
456            - const: ss_phy_irq
457
458additionalProperties: false
459
460examples:
461  - |
462    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
463    #include <dt-bindings/interrupt-controller/arm-gic.h>
464    #include <dt-bindings/interrupt-controller/irq.h>
465    soc {
466        #address-cells = <2>;
467        #size-cells = <2>;
468
469        usb@a6f8800 {
470            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
471            reg = <0 0x0a6f8800 0 0x400>;
472
473            #address-cells = <2>;
474            #size-cells = <2>;
475            ranges;
476            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
477                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
478                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
479                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
480                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
481            clock-names = "cfg_noc",
482                          "core",
483                          "iface",
484                          "sleep",
485                          "mock_utmi";
486
487            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
488                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
489            assigned-clock-rates = <19200000>, <150000000>;
490
491            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
492                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
493                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
494                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
495            interrupt-names = "hs_phy_irq", "ss_phy_irq",
496                          "dm_hs_phy_irq", "dp_hs_phy_irq";
497
498            power-domains = <&gcc USB30_PRIM_GDSC>;
499
500            resets = <&gcc GCC_USB30_PRIM_BCR>;
501
502            usb@a600000 {
503                compatible = "snps,dwc3";
504                reg = <0 0x0a600000 0 0xcd00>;
505                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
506                iommus = <&apps_smmu 0x740 0>;
507                snps,dis_u2_susphy_quirk;
508                snps,dis_enblslpm_quirk;
509                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
510                phy-names = "usb2-phy", "usb3-phy";
511            };
512        };
513    };
514