1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq6018-dwc3 18 - qcom,ipq8064-dwc3 19 - qcom,ipq8074-dwc3 20 - qcom,ipq9574-dwc3 21 - qcom,msm8953-dwc3 22 - qcom,msm8994-dwc3 23 - qcom,msm8996-dwc3 24 - qcom,msm8998-dwc3 25 - qcom,qcm2290-dwc3 26 - qcom,qcs404-dwc3 27 - qcom,sa8775p-dwc3 28 - qcom,sc7180-dwc3 29 - qcom,sc7280-dwc3 30 - qcom,sc8280xp-dwc3 31 - qcom,sdm660-dwc3 32 - qcom,sdm670-dwc3 33 - qcom,sdm845-dwc3 34 - qcom,sdx55-dwc3 35 - qcom,sdx65-dwc3 36 - qcom,sm4250-dwc3 37 - qcom,sm6115-dwc3 38 - qcom,sm6125-dwc3 39 - qcom,sm6350-dwc3 40 - qcom,sm6375-dwc3 41 - qcom,sm8150-dwc3 42 - qcom,sm8250-dwc3 43 - qcom,sm8350-dwc3 44 - qcom,sm8450-dwc3 45 - qcom,sm8550-dwc3 46 - const: qcom,dwc3 47 48 reg: 49 description: Offset and length of register set for QSCRATCH wrapper 50 maxItems: 1 51 52 "#address-cells": 53 enum: [ 1, 2 ] 54 55 "#size-cells": 56 enum: [ 1, 2 ] 57 58 ranges: true 59 60 power-domains: 61 description: specifies a phandle to PM domain provider node 62 maxItems: 1 63 64 required-opps: 65 maxItems: 1 66 67 clocks: 68 description: | 69 Several clocks are used, depending on the variant. Typical ones are:: 70 - cfg_noc:: System Config NOC clock. 71 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 72 60MHz for HS operation. 73 - iface:: System bus AXI clock. 74 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 75 power mode (U3). 76 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 77 mode. Its frequency should be 19.2MHz. 78 minItems: 1 79 maxItems: 9 80 81 clock-names: 82 minItems: 1 83 maxItems: 9 84 85 assigned-clocks: 86 items: 87 - description: Phandle and clock specifier of MOCK_UTMI_CLK. 88 - description: Phandle and clock specifoer of MASTER_CLK. 89 90 assigned-clock-rates: 91 items: 92 - description: Must be 19.2MHz (19200000). 93 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. 94 resets: 95 maxItems: 1 96 97 interconnects: 98 maxItems: 2 99 100 interconnect-names: 101 items: 102 - const: usb-ddr 103 - const: apps-usb 104 105 interrupts: 106 minItems: 1 107 maxItems: 4 108 109 interrupt-names: 110 minItems: 1 111 maxItems: 4 112 113 qcom,select-utmi-as-pipe-clk: 114 description: 115 If present, disable USB3 pipe_clk requirement. 116 Used when dwc3 operates without SSPHY and only 117 HS/FS/LS modes are supported. 118 type: boolean 119 120 wakeup-source: true 121 122# Required child node: 123 124patternProperties: 125 "^usb@[0-9a-f]+$": 126 $ref: snps,dwc3.yaml# 127 unevaluatedProperties: false 128 129 properties: 130 wakeup-source: false 131 132required: 133 - compatible 134 - reg 135 - "#address-cells" 136 - "#size-cells" 137 - ranges 138 - clocks 139 - clock-names 140 - interrupts 141 - interrupt-names 142 143allOf: 144 - if: 145 properties: 146 compatible: 147 contains: 148 enum: 149 - qcom,ipq4019-dwc3 150 then: 151 properties: 152 clocks: 153 maxItems: 3 154 clock-names: 155 items: 156 - const: core 157 - const: sleep 158 - const: mock_utmi 159 160 - if: 161 properties: 162 compatible: 163 contains: 164 enum: 165 - qcom,ipq8064-dwc3 166 then: 167 properties: 168 clocks: 169 items: 170 - description: Master/Core clock, has to be >= 125 MHz 171 for SS operation and >= 60MHz for HS operation. 172 clock-names: 173 items: 174 - const: core 175 176 - if: 177 properties: 178 compatible: 179 contains: 180 enum: 181 - qcom,ipq9574-dwc3 182 - qcom,msm8953-dwc3 183 - qcom,msm8996-dwc3 184 - qcom,msm8998-dwc3 185 - qcom,sa8775p-dwc3 186 - qcom,sc7180-dwc3 187 - qcom,sc7280-dwc3 188 - qcom,sdm670-dwc3 189 - qcom,sdm845-dwc3 190 - qcom,sdx55-dwc3 191 - qcom,sm6350-dwc3 192 then: 193 properties: 194 clocks: 195 maxItems: 5 196 clock-names: 197 items: 198 - const: cfg_noc 199 - const: core 200 - const: iface 201 - const: sleep 202 - const: mock_utmi 203 204 - if: 205 properties: 206 compatible: 207 contains: 208 enum: 209 - qcom,ipq6018-dwc3 210 then: 211 properties: 212 clocks: 213 minItems: 3 214 maxItems: 4 215 clock-names: 216 oneOf: 217 - items: 218 - const: core 219 - const: sleep 220 - const: mock_utmi 221 - items: 222 - const: cfg_noc 223 - const: core 224 - const: sleep 225 - const: mock_utmi 226 227 - if: 228 properties: 229 compatible: 230 contains: 231 enum: 232 - qcom,ipq8074-dwc3 233 then: 234 properties: 235 clocks: 236 maxItems: 4 237 clock-names: 238 items: 239 - const: cfg_noc 240 - const: core 241 - const: sleep 242 - const: mock_utmi 243 244 - if: 245 properties: 246 compatible: 247 contains: 248 enum: 249 - qcom,msm8994-dwc3 250 - qcom,qcs404-dwc3 251 then: 252 properties: 253 clocks: 254 maxItems: 4 255 clock-names: 256 items: 257 - const: core 258 - const: iface 259 - const: sleep 260 - const: mock_utmi 261 262 - if: 263 properties: 264 compatible: 265 contains: 266 enum: 267 - qcom,sc8280xp-dwc3 268 then: 269 properties: 270 clocks: 271 maxItems: 9 272 clock-names: 273 items: 274 - const: cfg_noc 275 - const: core 276 - const: iface 277 - const: sleep 278 - const: mock_utmi 279 - const: noc_aggr 280 - const: noc_aggr_north 281 - const: noc_aggr_south 282 - const: noc_sys 283 284 - if: 285 properties: 286 compatible: 287 contains: 288 enum: 289 - qcom,sdm660-dwc3 290 then: 291 properties: 292 clocks: 293 minItems: 6 294 clock-names: 295 items: 296 - const: cfg_noc 297 - const: core 298 - const: iface 299 - const: sleep 300 - const: mock_utmi 301 - const: bus 302 303 - if: 304 properties: 305 compatible: 306 contains: 307 enum: 308 - qcom,qcm2290-dwc3 309 - qcom,sm6115-dwc3 310 - qcom,sm6125-dwc3 311 - qcom,sm8150-dwc3 312 - qcom,sm8250-dwc3 313 - qcom,sm8450-dwc3 314 - qcom,sm8550-dwc3 315 then: 316 properties: 317 clocks: 318 minItems: 6 319 clock-names: 320 items: 321 - const: cfg_noc 322 - const: core 323 - const: iface 324 - const: sleep 325 - const: mock_utmi 326 - const: xo 327 328 - if: 329 properties: 330 compatible: 331 contains: 332 enum: 333 - qcom,sm8350-dwc3 334 then: 335 properties: 336 clocks: 337 minItems: 5 338 maxItems: 6 339 clock-names: 340 minItems: 5 341 items: 342 - const: cfg_noc 343 - const: core 344 - const: iface 345 - const: sleep 346 - const: mock_utmi 347 - const: xo 348 349 - if: 350 properties: 351 compatible: 352 contains: 353 enum: 354 - qcom,ipq4019-dwc3 355 - qcom,ipq6018-dwc3 356 - qcom,ipq8064-dwc3 357 - qcom,ipq8074-dwc3 358 - qcom,msm8994-dwc3 359 - qcom,qcs404-dwc3 360 - qcom,sc7180-dwc3 361 - qcom,sdm670-dwc3 362 - qcom,sdm845-dwc3 363 - qcom,sdx55-dwc3 364 - qcom,sdx65-dwc3 365 - qcom,sm4250-dwc3 366 - qcom,sm6125-dwc3 367 - qcom,sm6350-dwc3 368 - qcom,sm8150-dwc3 369 - qcom,sm8250-dwc3 370 - qcom,sm8350-dwc3 371 - qcom,sm8450-dwc3 372 - qcom,sm8550-dwc3 373 then: 374 properties: 375 interrupts: 376 items: 377 - description: The interrupt that is asserted 378 when a wakeup event is received on USB2 bus. 379 - description: The interrupt that is asserted 380 when a wakeup event is received on USB3 bus. 381 - description: Wakeup event on DM line. 382 - description: Wakeup event on DP line. 383 interrupt-names: 384 items: 385 - const: hs_phy_irq 386 - const: ss_phy_irq 387 - const: dm_hs_phy_irq 388 - const: dp_hs_phy_irq 389 390 - if: 391 properties: 392 compatible: 393 contains: 394 enum: 395 - qcom,msm8953-dwc3 396 - qcom,msm8996-dwc3 397 - qcom,msm8998-dwc3 398 - qcom,sm6115-dwc3 399 then: 400 properties: 401 interrupts: 402 maxItems: 2 403 interrupt-names: 404 items: 405 - const: hs_phy_irq 406 - const: ss_phy_irq 407 408 - if: 409 properties: 410 compatible: 411 contains: 412 enum: 413 - qcom,sdm660-dwc3 414 then: 415 properties: 416 interrupts: 417 minItems: 1 418 maxItems: 2 419 interrupt-names: 420 minItems: 1 421 items: 422 - const: hs_phy_irq 423 - const: ss_phy_irq 424 425 - if: 426 properties: 427 compatible: 428 contains: 429 enum: 430 - qcom,sc7280-dwc3 431 then: 432 properties: 433 interrupts: 434 minItems: 3 435 maxItems: 4 436 interrupt-names: 437 minItems: 3 438 items: 439 - const: hs_phy_irq 440 - const: dp_hs_phy_irq 441 - const: dm_hs_phy_irq 442 - const: ss_phy_irq 443 444 - if: 445 properties: 446 compatible: 447 contains: 448 enum: 449 - qcom,sc8280xp-dwc3 450 then: 451 properties: 452 interrupts: 453 maxItems: 4 454 interrupt-names: 455 items: 456 - const: pwr_event 457 - const: dp_hs_phy_irq 458 - const: dm_hs_phy_irq 459 - const: ss_phy_irq 460 461 - if: 462 properties: 463 compatible: 464 contains: 465 enum: 466 - qcom,sa8775p-dwc3 467 then: 468 properties: 469 interrupts: 470 minItems: 3 471 maxItems: 4 472 interrupt-names: 473 minItems: 3 474 items: 475 - const: pwr_event 476 - const: dp_hs_phy_irq 477 - const: dm_hs_phy_irq 478 - const: ss_phy_irq 479 480additionalProperties: false 481 482examples: 483 - | 484 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 485 #include <dt-bindings/interrupt-controller/arm-gic.h> 486 #include <dt-bindings/interrupt-controller/irq.h> 487 soc { 488 #address-cells = <2>; 489 #size-cells = <2>; 490 491 usb@a6f8800 { 492 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 493 reg = <0 0x0a6f8800 0 0x400>; 494 495 #address-cells = <2>; 496 #size-cells = <2>; 497 ranges; 498 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 499 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 500 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 501 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 502 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 503 clock-names = "cfg_noc", 504 "core", 505 "iface", 506 "sleep", 507 "mock_utmi"; 508 509 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 510 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 511 assigned-clock-rates = <19200000>, <150000000>; 512 513 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 517 interrupt-names = "hs_phy_irq", "ss_phy_irq", 518 "dm_hs_phy_irq", "dp_hs_phy_irq"; 519 520 power-domains = <&gcc USB30_PRIM_GDSC>; 521 522 resets = <&gcc GCC_USB30_PRIM_BCR>; 523 524 usb@a600000 { 525 compatible = "snps,dwc3"; 526 reg = <0 0x0a600000 0 0xcd00>; 527 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 528 iommus = <&apps_smmu 0x740 0>; 529 snps,dis_u2_susphy_quirk; 530 snps,dis_enblslpm_quirk; 531 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 532 phy-names = "usb2-phy", "usb3-phy"; 533 }; 534 }; 535 }; 536