1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Wesley Cheng <quic_wcheng@quicinc.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq4019-dwc3
17          - qcom,ipq6018-dwc3
18          - qcom,ipq8064-dwc3
19          - qcom,ipq8074-dwc3
20          - qcom,msm8953-dwc3
21          - qcom,msm8994-dwc3
22          - qcom,msm8996-dwc3
23          - qcom,msm8998-dwc3
24          - qcom,qcs404-dwc3
25          - qcom,sc7180-dwc3
26          - qcom,sc7280-dwc3
27          - qcom,sc8280xp-dwc3
28          - qcom,sdm660-dwc3
29          - qcom,sdm670-dwc3
30          - qcom,sdm845-dwc3
31          - qcom,sdx55-dwc3
32          - qcom,sdx65-dwc3
33          - qcom,sm4250-dwc3
34          - qcom,sm6115-dwc3
35          - qcom,sm6125-dwc3
36          - qcom,sm6350-dwc3
37          - qcom,sm6375-dwc3
38          - qcom,sm8150-dwc3
39          - qcom,sm8250-dwc3
40          - qcom,sm8350-dwc3
41          - qcom,sm8450-dwc3
42          - qcom,sm8550-dwc3
43      - const: qcom,dwc3
44
45  reg:
46    description: Offset and length of register set for QSCRATCH wrapper
47    maxItems: 1
48
49  "#address-cells":
50    enum: [ 1, 2 ]
51
52  "#size-cells":
53    enum: [ 1, 2 ]
54
55  ranges: true
56
57  power-domains:
58    description: specifies a phandle to PM domain provider node
59    maxItems: 1
60
61  clocks:
62    description: |
63      Several clocks are used, depending on the variant. Typical ones are::
64       - cfg_noc:: System Config NOC clock.
65       - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
66                60MHz for HS operation.
67       - iface:: System bus AXI clock.
68       - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
69                 power mode (U3).
70       - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
71                     mode. Its frequency should be 19.2MHz.
72    minItems: 1
73    maxItems: 9
74
75  clock-names:
76    minItems: 1
77    maxItems: 9
78
79  assigned-clocks:
80    items:
81      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
82      - description: Phandle and clock specifoer of MASTER_CLK.
83
84  assigned-clock-rates:
85    items:
86      - description: Must be 19.2MHz (19200000).
87      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
88  resets:
89    maxItems: 1
90
91  interconnects:
92    maxItems: 2
93
94  interconnect-names:
95    items:
96      - const: usb-ddr
97      - const: apps-usb
98
99  interrupts:
100    minItems: 1
101    maxItems: 4
102
103  interrupt-names:
104    minItems: 1
105    maxItems: 4
106
107  qcom,select-utmi-as-pipe-clk:
108    description:
109      If present, disable USB3 pipe_clk requirement.
110      Used when dwc3 operates without SSPHY and only
111      HS/FS/LS modes are supported.
112    type: boolean
113
114  wakeup-source: true
115
116# Required child node:
117
118patternProperties:
119  "^usb@[0-9a-f]+$":
120    $ref: snps,dwc3.yaml#
121
122    properties:
123      wakeup-source: false
124
125required:
126  - compatible
127  - reg
128  - "#address-cells"
129  - "#size-cells"
130  - ranges
131  - power-domains
132  - clocks
133  - clock-names
134  - interrupts
135  - interrupt-names
136
137allOf:
138  - if:
139      properties:
140        compatible:
141          contains:
142            enum:
143              - qcom,ipq4019-dwc3
144    then:
145      properties:
146        clocks:
147          maxItems: 3
148        clock-names:
149          items:
150            - const: core
151            - const: sleep
152            - const: mock_utmi
153
154  - if:
155      properties:
156        compatible:
157          contains:
158            enum:
159              - qcom,ipq8064-dwc3
160    then:
161      properties:
162        clocks:
163          items:
164            - description: Master/Core clock, has to be >= 125 MHz
165                for SS operation and >= 60MHz for HS operation.
166        clock-names:
167          items:
168            - const: core
169
170  - if:
171      properties:
172        compatible:
173          contains:
174            enum:
175              - qcom,msm8953-dwc3
176              - qcom,msm8996-dwc3
177              - qcom,msm8998-dwc3
178              - qcom,sc7180-dwc3
179              - qcom,sc7280-dwc3
180              - qcom,sdm670-dwc3
181              - qcom,sdm845-dwc3
182              - qcom,sdx55-dwc3
183              - qcom,sm6350-dwc3
184    then:
185      properties:
186        clocks:
187          maxItems: 5
188        clock-names:
189          items:
190            - const: cfg_noc
191            - const: core
192            - const: iface
193            - const: sleep
194            - const: mock_utmi
195
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - qcom,ipq6018-dwc3
202    then:
203      properties:
204        clocks:
205          minItems: 3
206          maxItems: 4
207        clock-names:
208          oneOf:
209            - items:
210                - const: core
211                - const: sleep
212                - const: mock_utmi
213            - items:
214                - const: cfg_noc
215                - const: core
216                - const: sleep
217                - const: mock_utmi
218
219  - if:
220      properties:
221        compatible:
222          contains:
223            enum:
224              - qcom,ipq8074-dwc3
225    then:
226      properties:
227        clocks:
228          maxItems: 4
229        clock-names:
230          items:
231            - const: cfg_noc
232            - const: core
233            - const: sleep
234            - const: mock_utmi
235
236  - if:
237      properties:
238        compatible:
239          contains:
240            enum:
241              - qcom,msm8994-dwc3
242              - qcom,qcs404-dwc3
243    then:
244      properties:
245        clocks:
246          maxItems: 4
247        clock-names:
248          items:
249            - const: core
250            - const: iface
251            - const: sleep
252            - const: mock_utmi
253
254  - if:
255      properties:
256        compatible:
257          contains:
258            enum:
259              - qcom,sc8280xp-dwc3
260    then:
261      properties:
262        clocks:
263          maxItems: 9
264        clock-names:
265          items:
266            - const: cfg_noc
267            - const: core
268            - const: iface
269            - const: sleep
270            - const: mock_utmi
271            - const: noc_aggr
272            - const: noc_aggr_north
273            - const: noc_aggr_south
274            - const: noc_sys
275
276  - if:
277      properties:
278        compatible:
279          contains:
280            enum:
281              - qcom,sdm660-dwc3
282    then:
283      properties:
284        clocks:
285          minItems: 6
286        clock-names:
287          items:
288            - const: cfg_noc
289            - const: core
290            - const: iface
291            - const: sleep
292            - const: mock_utmi
293            - const: bus
294
295  - if:
296      properties:
297        compatible:
298          contains:
299            enum:
300              - qcom,sm6115-dwc3
301              - qcom,sm6125-dwc3
302              - qcom,sm8150-dwc3
303              - qcom,sm8250-dwc3
304              - qcom,sm8450-dwc3
305              - qcom,sm8550-dwc3
306    then:
307      properties:
308        clocks:
309          minItems: 6
310        clock-names:
311          items:
312            - const: cfg_noc
313            - const: core
314            - const: iface
315            - const: sleep
316            - const: mock_utmi
317            - const: xo
318
319  - if:
320      properties:
321        compatible:
322          contains:
323            enum:
324              - qcom,sm8350-dwc3
325    then:
326      properties:
327        clocks:
328          minItems: 5
329          maxItems: 6
330        clock-names:
331          minItems: 5
332          items:
333            - const: cfg_noc
334            - const: core
335            - const: iface
336            - const: sleep
337            - const: mock_utmi
338            - const: xo
339
340  - if:
341      properties:
342        compatible:
343          contains:
344            enum:
345              - qcom,ipq4019-dwc3
346              - qcom,ipq6018-dwc3
347              - qcom,ipq8064-dwc3
348              - qcom,ipq8074-dwc3
349              - qcom,msm8994-dwc3
350              - qcom,qcs404-dwc3
351              - qcom,sc7180-dwc3
352              - qcom,sdm670-dwc3
353              - qcom,sdm845-dwc3
354              - qcom,sdx55-dwc3
355              - qcom,sdx65-dwc3
356              - qcom,sm4250-dwc3
357              - qcom,sm6125-dwc3
358              - qcom,sm6350-dwc3
359              - qcom,sm8150-dwc3
360              - qcom,sm8250-dwc3
361              - qcom,sm8350-dwc3
362              - qcom,sm8450-dwc3
363              - qcom,sm8550-dwc3
364    then:
365      properties:
366        interrupts:
367          items:
368            - description: The interrupt that is asserted
369                when a wakeup event is received on USB2 bus.
370            - description: The interrupt that is asserted
371                when a wakeup event is received on USB3 bus.
372            - description: Wakeup event on DM line.
373            - description: Wakeup event on DP line.
374        interrupt-names:
375          items:
376            - const: hs_phy_irq
377            - const: ss_phy_irq
378            - const: dm_hs_phy_irq
379            - const: dp_hs_phy_irq
380
381  - if:
382      properties:
383        compatible:
384          contains:
385            enum:
386              - qcom,msm8953-dwc3
387              - qcom,msm8996-dwc3
388              - qcom,msm8998-dwc3
389              - qcom,sm6115-dwc3
390    then:
391      properties:
392        interrupts:
393          maxItems: 2
394        interrupt-names:
395          items:
396            - const: hs_phy_irq
397            - const: ss_phy_irq
398
399  - if:
400      properties:
401        compatible:
402          contains:
403            enum:
404              - qcom,sdm660-dwc3
405    then:
406      properties:
407        interrupts:
408          minItems: 1
409          maxItems: 2
410        interrupt-names:
411          minItems: 1
412          items:
413            - const: hs_phy_irq
414            - const: ss_phy_irq
415
416  - if:
417      properties:
418        compatible:
419          contains:
420            enum:
421              - qcom,sc7280-dwc3
422    then:
423      properties:
424        interrupts:
425          minItems: 3
426          maxItems: 4
427        interrupt-names:
428          minItems: 3
429          items:
430            - const: hs_phy_irq
431            - const: dp_hs_phy_irq
432            - const: dm_hs_phy_irq
433            - const: ss_phy_irq
434
435  - if:
436      properties:
437        compatible:
438          contains:
439            enum:
440              - qcom,sc8280xp-dwc3
441    then:
442      properties:
443        interrupts:
444          maxItems: 4
445        interrupt-names:
446          items:
447            - const: pwr_event
448            - const: dp_hs_phy_irq
449            - const: dm_hs_phy_irq
450            - const: ss_phy_irq
451
452additionalProperties: false
453
454examples:
455  - |
456    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
457    #include <dt-bindings/interrupt-controller/arm-gic.h>
458    #include <dt-bindings/interrupt-controller/irq.h>
459    soc {
460        #address-cells = <2>;
461        #size-cells = <2>;
462
463        usb@a6f8800 {
464            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
465            reg = <0 0x0a6f8800 0 0x400>;
466
467            #address-cells = <2>;
468            #size-cells = <2>;
469            ranges;
470            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
471                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
472                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
473                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
474                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
475            clock-names = "cfg_noc",
476                          "core",
477                          "iface",
478                          "sleep",
479                          "mock_utmi";
480
481            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
482                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
483            assigned-clock-rates = <19200000>, <150000000>;
484
485            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
486                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
487                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
488                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
489            interrupt-names = "hs_phy_irq", "ss_phy_irq",
490                          "dm_hs_phy_irq", "dp_hs_phy_irq";
491
492            power-domains = <&gcc USB30_PRIM_GDSC>;
493
494            resets = <&gcc GCC_USB30_PRIM_BCR>;
495
496            usb@a600000 {
497                compatible = "snps,dwc3";
498                reg = <0 0x0a600000 0 0xcd00>;
499                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
500                iommus = <&apps_smmu 0x740 0>;
501                snps,dis_u2_susphy_quirk;
502                snps,dis_enblslpm_quirk;
503                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
504                phy-names = "usb2-phy", "usb3-phy";
505            };
506        };
507    };
508