1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq4019-dwc3
17          - qcom,ipq6018-dwc3
18          - qcom,ipq8064-dwc3
19          - qcom,msm8953-dwc3
20          - qcom,msm8996-dwc3
21          - qcom,msm8998-dwc3
22          - qcom,sc7180-dwc3
23          - qcom,sc7280-dwc3
24          - qcom,sdm660-dwc3
25          - qcom,sdm845-dwc3
26          - qcom,sdx55-dwc3
27          - qcom,sm4250-dwc3
28          - qcom,sm6115-dwc3
29          - qcom,sm6350-dwc3
30          - qcom,sm8150-dwc3
31          - qcom,sm8250-dwc3
32          - qcom,sm8350-dwc3
33          - qcom,sm8450-dwc3
34      - const: qcom,dwc3
35
36  reg:
37    description: Offset and length of register set for QSCRATCH wrapper
38    maxItems: 1
39
40  "#address-cells":
41    enum: [ 1, 2 ]
42
43  "#size-cells":
44    enum: [ 1, 2 ]
45
46  ranges: true
47
48  power-domains:
49    description: specifies a phandle to PM domain provider node
50    maxItems: 1
51
52  clocks:
53    description:
54      A list of phandle and clock-specifier pairs for the clocks
55      listed in clock-names.
56    items:
57      - description: System Config NOC clock.
58      - description: Master/Core clock, has to be >= 125 MHz
59          for SS operation and >= 60MHz for HS operation.
60      - description: System bus AXI clock.
61      - description: Mock utmi clock needed for ITP/SOF generation
62          in host mode. Its frequency should be 19.2MHz.
63      - description: Sleep clock, used for wakeup when
64          USB3 core goes into low power mode (U3).
65
66  clock-names:
67    items:
68      - const: cfg_noc
69      - const: core
70      - const: iface
71      - const: mock_utmi
72      - const: sleep
73
74  assigned-clocks:
75    items:
76      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
77      - description: Phandle and clock specifoer of MASTER_CLK.
78
79  assigned-clock-rates:
80    items:
81      - description: Must be 19.2MHz (19200000).
82      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
83  resets:
84    maxItems: 1
85
86  interconnects:
87    maxItems: 2
88
89  interconnect-names:
90    items:
91      - const: usb-ddr
92      - const: apps-usb
93
94  interrupts:
95    items:
96      - description: The interrupt that is asserted
97          when a wakeup event is received on USB2 bus.
98      - description: The interrupt that is asserted
99          when a wakeup event is received on USB3 bus.
100      - description: Wakeup event on DM line.
101      - description: Wakeup event on DP line.
102
103  interrupt-names:
104    items:
105      - const: hs_phy_irq
106      - const: ss_phy_irq
107      - const: dm_hs_phy_irq
108      - const: dp_hs_phy_irq
109
110  qcom,select-utmi-as-pipe-clk:
111    description:
112      If present, disable USB3 pipe_clk requirement.
113      Used when dwc3 operates without SSPHY and only
114      HS/FS/LS modes are supported.
115    type: boolean
116
117# Required child node:
118
119patternProperties:
120  "^usb@[0-9a-f]+$":
121    $ref: snps,dwc3.yaml#
122
123required:
124  - compatible
125  - reg
126  - "#address-cells"
127  - "#size-cells"
128  - ranges
129  - power-domains
130  - clocks
131  - clock-names
132  - interrupts
133  - interrupt-names
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/interrupt-controller/irq.h>
142    soc {
143        #address-cells = <2>;
144        #size-cells = <2>;
145
146        usb@a6f8800 {
147            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
148            reg = <0 0x0a6f8800 0 0x400>;
149
150            #address-cells = <2>;
151            #size-cells = <2>;
152            ranges;
153            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
154                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
155                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
156                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
157                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
158            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
159                      "sleep";
160
161            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
162                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
163            assigned-clock-rates = <19200000>, <150000000>;
164
165            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
166                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
167                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
168                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
169            interrupt-names = "hs_phy_irq", "ss_phy_irq",
170                          "dm_hs_phy_irq", "dp_hs_phy_irq";
171
172            power-domains = <&gcc USB30_PRIM_GDSC>;
173
174            resets = <&gcc GCC_USB30_PRIM_BCR>;
175
176            usb@a600000 {
177                compatible = "snps,dwc3";
178                reg = <0 0x0a600000 0 0xcd00>;
179                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
180                iommus = <&apps_smmu 0x740 0>;
181                snps,dis_u2_susphy_quirk;
182                snps,dis_enblslpm_quirk;
183                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
184                phy-names = "usb2-phy", "usb3-phy";
185            };
186        };
187    };
188