1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq6018-dwc3
17          - qcom,msm8996-dwc3
18          - qcom,msm8998-dwc3
19          - qcom,sc7180-dwc3
20          - qcom,sc7280-dwc3
21          - qcom,sdm660-dwc3
22          - qcom,sdm845-dwc3
23          - qcom,sdx55-dwc3
24          - qcom,sm4250-dwc3
25          - qcom,sm6115-dwc3
26          - qcom,sm8150-dwc3
27          - qcom,sm8250-dwc3
28          - qcom,sm8350-dwc3
29      - const: qcom,dwc3
30
31  reg:
32    description: Offset and length of register set for QSCRATCH wrapper
33    maxItems: 1
34
35  "#address-cells":
36    enum: [ 1, 2 ]
37
38  "#size-cells":
39    enum: [ 1, 2 ]
40
41  ranges: true
42
43  power-domains:
44    description: specifies a phandle to PM domain provider node
45    maxItems: 1
46
47  clocks:
48    description:
49      A list of phandle and clock-specifier pairs for the clocks
50      listed in clock-names.
51    items:
52      - description: System Config NOC clock.
53      - description: Master/Core clock, has to be >= 125 MHz
54          for SS operation and >= 60MHz for HS operation.
55      - description: System bus AXI clock.
56      - description: Mock utmi clock needed for ITP/SOF generation
57          in host mode. Its frequency should be 19.2MHz.
58      - description: Sleep clock, used for wakeup when
59          USB3 core goes into low power mode (U3).
60
61  clock-names:
62    items:
63      - const: cfg_noc
64      - const: core
65      - const: iface
66      - const: mock_utmi
67      - const: sleep
68
69  assigned-clocks:
70    items:
71      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
72      - description: Phandle and clock specifoer of MASTER_CLK.
73
74  assigned-clock-rates:
75    items:
76      - description: Must be 19.2MHz (19200000).
77      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
78  resets:
79    maxItems: 1
80
81  interconnects:
82    maxItems: 2
83
84  interconnect-names:
85    items:
86      - const: usb-ddr
87      - const: apps-usb
88
89  interrupts:
90    items:
91      - description: The interrupt that is asserted
92          when a wakeup event is received on USB2 bus.
93      - description: The interrupt that is asserted
94          when a wakeup event is received on USB3 bus.
95      - description: Wakeup event on DM line.
96      - description: Wakeup event on DP line.
97
98  interrupt-names:
99    items:
100      - const: hs_phy_irq
101      - const: ss_phy_irq
102      - const: dm_hs_phy_irq
103      - const: dp_hs_phy_irq
104
105  qcom,select-utmi-as-pipe-clk:
106    description:
107      If present, disable USB3 pipe_clk requirement.
108      Used when dwc3 operates without SSPHY and only
109      HS/FS/LS modes are supported.
110    type: boolean
111
112# Required child node:
113
114patternProperties:
115  "^usb@[0-9a-f]+$":
116    $ref: snps,dwc3.yaml#
117
118required:
119  - compatible
120  - reg
121  - "#address-cells"
122  - "#size-cells"
123  - ranges
124  - power-domains
125  - clocks
126  - clock-names
127  - interrupts
128  - interrupt-names
129
130additionalProperties: false
131
132examples:
133  - |
134    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136    #include <dt-bindings/interrupt-controller/irq.h>
137    soc {
138        #address-cells = <2>;
139        #size-cells = <2>;
140
141        usb@a6f8800 {
142            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
143            reg = <0 0x0a6f8800 0 0x400>;
144
145            #address-cells = <2>;
146            #size-cells = <2>;
147            ranges;
148            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
149                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
150                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
151                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
152                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
153            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
154                      "sleep";
155
156            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
157                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
158            assigned-clock-rates = <19200000>, <150000000>;
159
160            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
161                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
162                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
163                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
164            interrupt-names = "hs_phy_irq", "ss_phy_irq",
165                          "dm_hs_phy_irq", "dp_hs_phy_irq";
166
167            power-domains = <&gcc USB30_PRIM_GDSC>;
168
169            resets = <&gcc GCC_USB30_PRIM_BCR>;
170
171            usb@a600000 {
172                compatible = "snps,dwc3";
173                reg = <0 0x0a600000 0 0xcd00>;
174                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
175                iommus = <&apps_smmu 0x740 0>;
176                snps,dis_u2_susphy_quirk;
177                snps,dis_enblslpm_quirk;
178                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
179                phy-names = "usb2-phy", "usb3-phy";
180            };
181        };
182    };
183