1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,msm8996-dwc3
17          - qcom,msm8998-dwc3
18          - qcom,sc7180-dwc3
19          - qcom,sdm845-dwc3
20      - const: qcom,dwc3
21
22  reg:
23    description: Offset and length of register set for QSCRATCH wrapper
24    maxItems: 1
25
26  "#address-cells":
27    enum: [ 1, 2 ]
28
29  "#size-cells":
30    enum: [ 1, 2 ]
31
32  ranges: true
33
34  power-domains:
35    description: specifies a phandle to PM domain provider node
36    maxItems: 1
37
38  clocks:
39    description:
40      A list of phandle and clock-specifier pairs for the clocks
41      listed in clock-names.
42    items:
43      - description: System Config NOC clock.
44      - description: Master/Core clock, has to be >= 125 MHz
45          for SS operation and >= 60MHz for HS operation.
46      - description: System bus AXI clock.
47      - description: Mock utmi clock needed for ITP/SOF generation
48          in host mode. Its frequency should be 19.2MHz.
49      - description: Sleep clock, used for wakeup when
50          USB3 core goes into low power mode (U3).
51
52  clock-names:
53    items:
54      - const: cfg_noc
55      - const: core
56      - const: iface
57      - const: mock_utmi
58      - const: sleep
59
60  assigned-clocks:
61    items:
62      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
63      - description: Phandle and clock specifoer of MASTER_CLK.
64
65  assigned-clock-rates:
66    items:
67      - description: Must be 19.2MHz (19200000).
68      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
69  resets:
70    maxItems: 1
71
72  interrupts:
73    items:
74      - description: The interrupt that is asserted
75          when a wakeup event is received on USB2 bus.
76      - description: The interrupt that is asserted
77          when a wakeup event is received on USB3 bus.
78      - description: Wakeup event on DM line.
79      - description: Wakeup event on DP line.
80
81  interrupt-names:
82    items:
83      - const: hs_phy_irq
84      - const: ss_phy_irq
85      - const: dm_hs_phy_irq
86      - const: dp_hs_phy_irq
87
88  qcom,select-utmi-as-pipe-clk:
89    description:
90      If present, disable USB3 pipe_clk requirement.
91      Used when dwc3 operates without SSPHY and only
92      HS/FS/LS modes are supported.
93    type: boolean
94
95# Required child node:
96
97patternProperties:
98  "^dwc3@[0-9a-f]+$":
99    type: object
100    description:
101      A child node must exist to represent the core DWC3 IP block
102      The content of the node is defined in dwc3.txt.
103
104required:
105  - compatible
106  - reg
107  - "#address-cells"
108  - "#size-cells"
109  - ranges
110  - power-domains
111  - clocks
112  - clock-names
113  - interrupts
114  - interrupt-names
115
116examples:
117  - |
118    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
119    #include <dt-bindings/interrupt-controller/arm-gic.h>
120    #include <dt-bindings/interrupt-controller/irq.h>
121    soc {
122        #address-cells = <2>;
123        #size-cells = <2>;
124
125        usb@a6f8800 {
126            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
127            reg = <0 0x0a6f8800 0 0x400>;
128
129            #address-cells = <2>;
130            #size-cells = <2>;
131            ranges;
132            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
133                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
134                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
135                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
136                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
137            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
138                      "sleep";
139
140            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
141                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
142            assigned-clock-rates = <19200000>, <150000000>;
143
144            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
145                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
146                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
147                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
148            interrupt-names = "hs_phy_irq", "ss_phy_irq",
149                          "dm_hs_phy_irq", "dp_hs_phy_irq";
150
151            power-domains = <&gcc USB30_PRIM_GDSC>;
152
153            resets = <&gcc GCC_USB30_PRIM_BCR>;
154
155            dwc3@a600000 {
156                compatible = "snps,dwc3";
157                reg = <0 0x0a600000 0 0xcd00>;
158                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
159                iommus = <&apps_smmu 0x740 0>;
160                snps,dis_u2_susphy_quirk;
161                snps,dis_enblslpm_quirk;
162                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
163                phy-names = "usb2-phy", "usb3-phy";
164            };
165        };
166    };
167