1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Wesley Cheng <quic_wcheng@quicinc.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq4019-dwc3
17          - qcom,ipq6018-dwc3
18          - qcom,ipq8064-dwc3
19          - qcom,ipq8074-dwc3
20          - qcom,msm8953-dwc3
21          - qcom,msm8994-dwc3
22          - qcom,msm8996-dwc3
23          - qcom,msm8998-dwc3
24          - qcom,qcs404-dwc3
25          - qcom,sc7180-dwc3
26          - qcom,sc7280-dwc3
27          - qcom,sc8280xp-dwc3
28          - qcom,sdm660-dwc3
29          - qcom,sdm670-dwc3
30          - qcom,sdm845-dwc3
31          - qcom,sdx55-dwc3
32          - qcom,sdx65-dwc3
33          - qcom,sm4250-dwc3
34          - qcom,sm6115-dwc3
35          - qcom,sm6125-dwc3
36          - qcom,sm6350-dwc3
37          - qcom,sm6375-dwc3
38          - qcom,sm8150-dwc3
39          - qcom,sm8250-dwc3
40          - qcom,sm8350-dwc3
41          - qcom,sm8450-dwc3
42          - qcom,sm8550-dwc3
43      - const: qcom,dwc3
44
45  reg:
46    description: Offset and length of register set for QSCRATCH wrapper
47    maxItems: 1
48
49  "#address-cells":
50    enum: [ 1, 2 ]
51
52  "#size-cells":
53    enum: [ 1, 2 ]
54
55  ranges: true
56
57  power-domains:
58    description: specifies a phandle to PM domain provider node
59    maxItems: 1
60
61  required-opps:
62    maxItems: 1
63
64  clocks:
65    description: |
66      Several clocks are used, depending on the variant. Typical ones are::
67       - cfg_noc:: System Config NOC clock.
68       - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
69                60MHz for HS operation.
70       - iface:: System bus AXI clock.
71       - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
72                 power mode (U3).
73       - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
74                     mode. Its frequency should be 19.2MHz.
75    minItems: 1
76    maxItems: 9
77
78  clock-names:
79    minItems: 1
80    maxItems: 9
81
82  assigned-clocks:
83    items:
84      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
85      - description: Phandle and clock specifoer of MASTER_CLK.
86
87  assigned-clock-rates:
88    items:
89      - description: Must be 19.2MHz (19200000).
90      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
91  resets:
92    maxItems: 1
93
94  interconnects:
95    maxItems: 2
96
97  interconnect-names:
98    items:
99      - const: usb-ddr
100      - const: apps-usb
101
102  interrupts:
103    minItems: 1
104    maxItems: 4
105
106  interrupt-names:
107    minItems: 1
108    maxItems: 4
109
110  qcom,select-utmi-as-pipe-clk:
111    description:
112      If present, disable USB3 pipe_clk requirement.
113      Used when dwc3 operates without SSPHY and only
114      HS/FS/LS modes are supported.
115    type: boolean
116
117  wakeup-source: true
118
119# Required child node:
120
121patternProperties:
122  "^usb@[0-9a-f]+$":
123    $ref: snps,dwc3.yaml#
124    unevaluatedProperties: false
125
126    properties:
127      wakeup-source: false
128
129required:
130  - compatible
131  - reg
132  - "#address-cells"
133  - "#size-cells"
134  - ranges
135  - power-domains
136  - clocks
137  - clock-names
138  - interrupts
139  - interrupt-names
140
141allOf:
142  - if:
143      properties:
144        compatible:
145          contains:
146            enum:
147              - qcom,ipq4019-dwc3
148    then:
149      properties:
150        clocks:
151          maxItems: 3
152        clock-names:
153          items:
154            - const: core
155            - const: sleep
156            - const: mock_utmi
157
158  - if:
159      properties:
160        compatible:
161          contains:
162            enum:
163              - qcom,ipq8064-dwc3
164    then:
165      properties:
166        clocks:
167          items:
168            - description: Master/Core clock, has to be >= 125 MHz
169                for SS operation and >= 60MHz for HS operation.
170        clock-names:
171          items:
172            - const: core
173
174  - if:
175      properties:
176        compatible:
177          contains:
178            enum:
179              - qcom,msm8953-dwc3
180              - qcom,msm8996-dwc3
181              - qcom,msm8998-dwc3
182              - qcom,sc7180-dwc3
183              - qcom,sc7280-dwc3
184              - qcom,sdm670-dwc3
185              - qcom,sdm845-dwc3
186              - qcom,sdx55-dwc3
187              - qcom,sm6350-dwc3
188    then:
189      properties:
190        clocks:
191          maxItems: 5
192        clock-names:
193          items:
194            - const: cfg_noc
195            - const: core
196            - const: iface
197            - const: sleep
198            - const: mock_utmi
199
200  - if:
201      properties:
202        compatible:
203          contains:
204            enum:
205              - qcom,ipq6018-dwc3
206    then:
207      properties:
208        clocks:
209          minItems: 3
210          maxItems: 4
211        clock-names:
212          oneOf:
213            - items:
214                - const: core
215                - const: sleep
216                - const: mock_utmi
217            - items:
218                - const: cfg_noc
219                - const: core
220                - const: sleep
221                - const: mock_utmi
222
223  - if:
224      properties:
225        compatible:
226          contains:
227            enum:
228              - qcom,ipq8074-dwc3
229    then:
230      properties:
231        clocks:
232          maxItems: 4
233        clock-names:
234          items:
235            - const: cfg_noc
236            - const: core
237            - const: sleep
238            - const: mock_utmi
239
240  - if:
241      properties:
242        compatible:
243          contains:
244            enum:
245              - qcom,msm8994-dwc3
246              - qcom,qcs404-dwc3
247    then:
248      properties:
249        clocks:
250          maxItems: 4
251        clock-names:
252          items:
253            - const: core
254            - const: iface
255            - const: sleep
256            - const: mock_utmi
257
258  - if:
259      properties:
260        compatible:
261          contains:
262            enum:
263              - qcom,sc8280xp-dwc3
264    then:
265      properties:
266        clocks:
267          maxItems: 9
268        clock-names:
269          items:
270            - const: cfg_noc
271            - const: core
272            - const: iface
273            - const: sleep
274            - const: mock_utmi
275            - const: noc_aggr
276            - const: noc_aggr_north
277            - const: noc_aggr_south
278            - const: noc_sys
279
280  - if:
281      properties:
282        compatible:
283          contains:
284            enum:
285              - qcom,sdm660-dwc3
286    then:
287      properties:
288        clocks:
289          minItems: 6
290        clock-names:
291          items:
292            - const: cfg_noc
293            - const: core
294            - const: iface
295            - const: sleep
296            - const: mock_utmi
297            - const: bus
298
299  - if:
300      properties:
301        compatible:
302          contains:
303            enum:
304              - qcom,sm6115-dwc3
305              - qcom,sm6125-dwc3
306              - qcom,sm8150-dwc3
307              - qcom,sm8250-dwc3
308              - qcom,sm8450-dwc3
309              - qcom,sm8550-dwc3
310    then:
311      properties:
312        clocks:
313          minItems: 6
314        clock-names:
315          items:
316            - const: cfg_noc
317            - const: core
318            - const: iface
319            - const: sleep
320            - const: mock_utmi
321            - const: xo
322
323  - if:
324      properties:
325        compatible:
326          contains:
327            enum:
328              - qcom,sm8350-dwc3
329    then:
330      properties:
331        clocks:
332          minItems: 5
333          maxItems: 6
334        clock-names:
335          minItems: 5
336          items:
337            - const: cfg_noc
338            - const: core
339            - const: iface
340            - const: sleep
341            - const: mock_utmi
342            - const: xo
343
344  - if:
345      properties:
346        compatible:
347          contains:
348            enum:
349              - qcom,ipq4019-dwc3
350              - qcom,ipq6018-dwc3
351              - qcom,ipq8064-dwc3
352              - qcom,ipq8074-dwc3
353              - qcom,msm8994-dwc3
354              - qcom,qcs404-dwc3
355              - qcom,sc7180-dwc3
356              - qcom,sdm670-dwc3
357              - qcom,sdm845-dwc3
358              - qcom,sdx55-dwc3
359              - qcom,sdx65-dwc3
360              - qcom,sm4250-dwc3
361              - qcom,sm6125-dwc3
362              - qcom,sm6350-dwc3
363              - qcom,sm8150-dwc3
364              - qcom,sm8250-dwc3
365              - qcom,sm8350-dwc3
366              - qcom,sm8450-dwc3
367              - qcom,sm8550-dwc3
368    then:
369      properties:
370        interrupts:
371          items:
372            - description: The interrupt that is asserted
373                when a wakeup event is received on USB2 bus.
374            - description: The interrupt that is asserted
375                when a wakeup event is received on USB3 bus.
376            - description: Wakeup event on DM line.
377            - description: Wakeup event on DP line.
378        interrupt-names:
379          items:
380            - const: hs_phy_irq
381            - const: ss_phy_irq
382            - const: dm_hs_phy_irq
383            - const: dp_hs_phy_irq
384
385  - if:
386      properties:
387        compatible:
388          contains:
389            enum:
390              - qcom,msm8953-dwc3
391              - qcom,msm8996-dwc3
392              - qcom,msm8998-dwc3
393              - qcom,sm6115-dwc3
394    then:
395      properties:
396        interrupts:
397          maxItems: 2
398        interrupt-names:
399          items:
400            - const: hs_phy_irq
401            - const: ss_phy_irq
402
403  - if:
404      properties:
405        compatible:
406          contains:
407            enum:
408              - qcom,sdm660-dwc3
409    then:
410      properties:
411        interrupts:
412          minItems: 1
413          maxItems: 2
414        interrupt-names:
415          minItems: 1
416          items:
417            - const: hs_phy_irq
418            - const: ss_phy_irq
419
420  - if:
421      properties:
422        compatible:
423          contains:
424            enum:
425              - qcom,sc7280-dwc3
426    then:
427      properties:
428        interrupts:
429          minItems: 3
430          maxItems: 4
431        interrupt-names:
432          minItems: 3
433          items:
434            - const: hs_phy_irq
435            - const: dp_hs_phy_irq
436            - const: dm_hs_phy_irq
437            - const: ss_phy_irq
438
439  - if:
440      properties:
441        compatible:
442          contains:
443            enum:
444              - qcom,sc8280xp-dwc3
445    then:
446      properties:
447        interrupts:
448          maxItems: 4
449        interrupt-names:
450          items:
451            - const: pwr_event
452            - const: dp_hs_phy_irq
453            - const: dm_hs_phy_irq
454            - const: ss_phy_irq
455
456additionalProperties: false
457
458examples:
459  - |
460    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
461    #include <dt-bindings/interrupt-controller/arm-gic.h>
462    #include <dt-bindings/interrupt-controller/irq.h>
463    soc {
464        #address-cells = <2>;
465        #size-cells = <2>;
466
467        usb@a6f8800 {
468            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
469            reg = <0 0x0a6f8800 0 0x400>;
470
471            #address-cells = <2>;
472            #size-cells = <2>;
473            ranges;
474            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
475                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
476                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
477                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
478                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
479            clock-names = "cfg_noc",
480                          "core",
481                          "iface",
482                          "sleep",
483                          "mock_utmi";
484
485            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
486                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
487            assigned-clock-rates = <19200000>, <150000000>;
488
489            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
490                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
491                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
492                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
493            interrupt-names = "hs_phy_irq", "ss_phy_irq",
494                          "dm_hs_phy_irq", "dp_hs_phy_irq";
495
496            power-domains = <&gcc USB30_PRIM_GDSC>;
497
498            resets = <&gcc GCC_USB30_PRIM_BCR>;
499
500            usb@a600000 {
501                compatible = "snps,dwc3";
502                reg = <0 0x0a600000 0 0xcd00>;
503                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
504                iommus = <&apps_smmu 0x740 0>;
505                snps,dis_u2_susphy_quirk;
506                snps,dis_enblslpm_quirk;
507                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
508                phy-names = "usb2-phy", "usb3-phy";
509            };
510        };
511    };
512