1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq5332-dwc3 18 - qcom,ipq6018-dwc3 19 - qcom,ipq8064-dwc3 20 - qcom,ipq8074-dwc3 21 - qcom,ipq9574-dwc3 22 - qcom,msm8953-dwc3 23 - qcom,msm8994-dwc3 24 - qcom,msm8996-dwc3 25 - qcom,msm8998-dwc3 26 - qcom,qcm2290-dwc3 27 - qcom,qcs404-dwc3 28 - qcom,sa8775p-dwc3 29 - qcom,sc7180-dwc3 30 - qcom,sc7280-dwc3 31 - qcom,sc8280xp-dwc3 32 - qcom,sdm660-dwc3 33 - qcom,sdm670-dwc3 34 - qcom,sdm845-dwc3 35 - qcom,sdx55-dwc3 36 - qcom,sdx65-dwc3 37 - qcom,sm4250-dwc3 38 - qcom,sm6115-dwc3 39 - qcom,sm6125-dwc3 40 - qcom,sm6350-dwc3 41 - qcom,sm6375-dwc3 42 - qcom,sm8150-dwc3 43 - qcom,sm8250-dwc3 44 - qcom,sm8350-dwc3 45 - qcom,sm8450-dwc3 46 - qcom,sm8550-dwc3 47 - const: qcom,dwc3 48 49 reg: 50 description: Offset and length of register set for QSCRATCH wrapper 51 maxItems: 1 52 53 "#address-cells": 54 enum: [ 1, 2 ] 55 56 "#size-cells": 57 enum: [ 1, 2 ] 58 59 ranges: true 60 61 power-domains: 62 description: specifies a phandle to PM domain provider node 63 maxItems: 1 64 65 required-opps: 66 maxItems: 1 67 68 clocks: 69 description: | 70 Several clocks are used, depending on the variant. Typical ones are:: 71 - cfg_noc:: System Config NOC clock. 72 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 73 60MHz for HS operation. 74 - iface:: System bus AXI clock. 75 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 76 power mode (U3). 77 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 78 mode. Its frequency should be 19.2MHz. 79 minItems: 1 80 maxItems: 9 81 82 clock-names: 83 minItems: 1 84 maxItems: 9 85 86 resets: 87 maxItems: 1 88 89 interconnects: 90 maxItems: 2 91 92 interconnect-names: 93 items: 94 - const: usb-ddr 95 - const: apps-usb 96 97 interrupts: 98 minItems: 1 99 maxItems: 4 100 101 interrupt-names: 102 minItems: 1 103 maxItems: 4 104 105 qcom,select-utmi-as-pipe-clk: 106 description: 107 If present, disable USB3 pipe_clk requirement. 108 Used when dwc3 operates without SSPHY and only 109 HS/FS/LS modes are supported. 110 type: boolean 111 112 wakeup-source: true 113 114# Required child node: 115 116patternProperties: 117 "^usb@[0-9a-f]+$": 118 $ref: snps,dwc3.yaml# 119 unevaluatedProperties: false 120 121 properties: 122 wakeup-source: false 123 124required: 125 - compatible 126 - reg 127 - "#address-cells" 128 - "#size-cells" 129 - ranges 130 - clocks 131 - clock-names 132 - interrupts 133 - interrupt-names 134 135allOf: 136 - if: 137 properties: 138 compatible: 139 contains: 140 enum: 141 - qcom,ipq4019-dwc3 142 then: 143 properties: 144 clocks: 145 maxItems: 3 146 clock-names: 147 items: 148 - const: core 149 - const: sleep 150 - const: mock_utmi 151 152 - if: 153 properties: 154 compatible: 155 contains: 156 enum: 157 - qcom,ipq8064-dwc3 158 then: 159 properties: 160 clocks: 161 items: 162 - description: Master/Core clock, has to be >= 125 MHz 163 for SS operation and >= 60MHz for HS operation. 164 clock-names: 165 items: 166 - const: core 167 168 - if: 169 properties: 170 compatible: 171 contains: 172 enum: 173 - qcom,ipq9574-dwc3 174 - qcom,msm8953-dwc3 175 - qcom,msm8996-dwc3 176 - qcom,msm8998-dwc3 177 - qcom,sa8775p-dwc3 178 - qcom,sc7180-dwc3 179 - qcom,sc7280-dwc3 180 - qcom,sdm670-dwc3 181 - qcom,sdm845-dwc3 182 - qcom,sdx55-dwc3 183 - qcom,sm6350-dwc3 184 then: 185 properties: 186 clocks: 187 maxItems: 5 188 clock-names: 189 items: 190 - const: cfg_noc 191 - const: core 192 - const: iface 193 - const: sleep 194 - const: mock_utmi 195 196 - if: 197 properties: 198 compatible: 199 contains: 200 enum: 201 - qcom,ipq6018-dwc3 202 then: 203 properties: 204 clocks: 205 minItems: 3 206 maxItems: 4 207 clock-names: 208 oneOf: 209 - items: 210 - const: core 211 - const: sleep 212 - const: mock_utmi 213 - items: 214 - const: cfg_noc 215 - const: core 216 - const: sleep 217 - const: mock_utmi 218 219 - if: 220 properties: 221 compatible: 222 contains: 223 enum: 224 - qcom,ipq8074-dwc3 225 then: 226 properties: 227 clocks: 228 maxItems: 4 229 clock-names: 230 items: 231 - const: cfg_noc 232 - const: core 233 - const: sleep 234 - const: mock_utmi 235 236 - if: 237 properties: 238 compatible: 239 contains: 240 enum: 241 - qcom,ipq5332-dwc3 242 - qcom,msm8994-dwc3 243 - qcom,qcs404-dwc3 244 then: 245 properties: 246 clocks: 247 maxItems: 4 248 clock-names: 249 items: 250 - const: core 251 - const: iface 252 - const: sleep 253 - const: mock_utmi 254 255 - if: 256 properties: 257 compatible: 258 contains: 259 enum: 260 - qcom,sc8280xp-dwc3 261 then: 262 properties: 263 clocks: 264 maxItems: 9 265 clock-names: 266 items: 267 - const: cfg_noc 268 - const: core 269 - const: iface 270 - const: sleep 271 - const: mock_utmi 272 - const: noc_aggr 273 - const: noc_aggr_north 274 - const: noc_aggr_south 275 - const: noc_sys 276 277 - if: 278 properties: 279 compatible: 280 contains: 281 enum: 282 - qcom,sdm660-dwc3 283 then: 284 properties: 285 clocks: 286 minItems: 5 287 maxItems: 6 288 clock-names: 289 oneOf: 290 - items: 291 - const: cfg_noc 292 - const: core 293 - const: iface 294 - const: sleep 295 - const: mock_utmi 296 - const: bus 297 - items: 298 - const: cfg_noc 299 - const: core 300 - const: sleep 301 - const: mock_utmi 302 - const: bus 303 304 - if: 305 properties: 306 compatible: 307 contains: 308 enum: 309 - qcom,qcm2290-dwc3 310 - qcom,sm6115-dwc3 311 - qcom,sm6125-dwc3 312 - qcom,sm8150-dwc3 313 - qcom,sm8250-dwc3 314 - qcom,sm8450-dwc3 315 - qcom,sm8550-dwc3 316 then: 317 properties: 318 clocks: 319 minItems: 6 320 clock-names: 321 items: 322 - const: cfg_noc 323 - const: core 324 - const: iface 325 - const: sleep 326 - const: mock_utmi 327 - const: xo 328 329 - if: 330 properties: 331 compatible: 332 contains: 333 enum: 334 - qcom,sm8350-dwc3 335 then: 336 properties: 337 clocks: 338 minItems: 5 339 maxItems: 6 340 clock-names: 341 minItems: 5 342 items: 343 - const: cfg_noc 344 - const: core 345 - const: iface 346 - const: sleep 347 - const: mock_utmi 348 - const: xo 349 350 - if: 351 properties: 352 compatible: 353 contains: 354 enum: 355 - qcom,ipq4019-dwc3 356 - qcom,ipq6018-dwc3 357 - qcom,ipq8064-dwc3 358 - qcom,ipq8074-dwc3 359 - qcom,msm8994-dwc3 360 - qcom,qcs404-dwc3 361 - qcom,sc7180-dwc3 362 - qcom,sdm670-dwc3 363 - qcom,sdm845-dwc3 364 - qcom,sdx55-dwc3 365 - qcom,sdx65-dwc3 366 - qcom,sm4250-dwc3 367 - qcom,sm6125-dwc3 368 - qcom,sm6350-dwc3 369 - qcom,sm8150-dwc3 370 - qcom,sm8250-dwc3 371 - qcom,sm8350-dwc3 372 - qcom,sm8450-dwc3 373 - qcom,sm8550-dwc3 374 then: 375 properties: 376 interrupts: 377 items: 378 - description: The interrupt that is asserted 379 when a wakeup event is received on USB2 bus. 380 - description: The interrupt that is asserted 381 when a wakeup event is received on USB3 bus. 382 - description: Wakeup event on DM line. 383 - description: Wakeup event on DP line. 384 interrupt-names: 385 items: 386 - const: hs_phy_irq 387 - const: ss_phy_irq 388 - const: dm_hs_phy_irq 389 - const: dp_hs_phy_irq 390 391 - if: 392 properties: 393 compatible: 394 contains: 395 enum: 396 - qcom,msm8953-dwc3 397 - qcom,msm8996-dwc3 398 - qcom,msm8998-dwc3 399 - qcom,sm6115-dwc3 400 then: 401 properties: 402 interrupts: 403 maxItems: 2 404 interrupt-names: 405 items: 406 - const: hs_phy_irq 407 - const: ss_phy_irq 408 409 - if: 410 properties: 411 compatible: 412 contains: 413 enum: 414 - qcom,ipq5332-dwc3 415 - qcom,sdm660-dwc3 416 then: 417 properties: 418 interrupts: 419 minItems: 1 420 maxItems: 2 421 interrupt-names: 422 minItems: 1 423 items: 424 - const: hs_phy_irq 425 - const: ss_phy_irq 426 427 - if: 428 properties: 429 compatible: 430 contains: 431 enum: 432 - qcom,sc7280-dwc3 433 then: 434 properties: 435 interrupts: 436 minItems: 3 437 maxItems: 4 438 interrupt-names: 439 minItems: 3 440 items: 441 - const: hs_phy_irq 442 - const: dp_hs_phy_irq 443 - const: dm_hs_phy_irq 444 - const: ss_phy_irq 445 446 - if: 447 properties: 448 compatible: 449 contains: 450 enum: 451 - qcom,sc8280xp-dwc3 452 then: 453 properties: 454 interrupts: 455 maxItems: 4 456 interrupt-names: 457 items: 458 - const: pwr_event 459 - const: dp_hs_phy_irq 460 - const: dm_hs_phy_irq 461 - const: ss_phy_irq 462 463 - if: 464 properties: 465 compatible: 466 contains: 467 enum: 468 - qcom,sa8775p-dwc3 469 then: 470 properties: 471 interrupts: 472 minItems: 3 473 maxItems: 4 474 interrupt-names: 475 minItems: 3 476 items: 477 - const: pwr_event 478 - const: dp_hs_phy_irq 479 - const: dm_hs_phy_irq 480 - const: ss_phy_irq 481 482additionalProperties: false 483 484examples: 485 - | 486 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 487 #include <dt-bindings/interrupt-controller/arm-gic.h> 488 #include <dt-bindings/interrupt-controller/irq.h> 489 soc { 490 #address-cells = <2>; 491 #size-cells = <2>; 492 493 usb@a6f8800 { 494 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 495 reg = <0 0x0a6f8800 0 0x400>; 496 497 #address-cells = <2>; 498 #size-cells = <2>; 499 ranges; 500 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 501 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 502 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 503 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 504 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 505 clock-names = "cfg_noc", 506 "core", 507 "iface", 508 "sleep", 509 "mock_utmi"; 510 511 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 512 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 513 assigned-clock-rates = <19200000>, <150000000>; 514 515 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "hs_phy_irq", "ss_phy_irq", 520 "dm_hs_phy_irq", "dp_hs_phy_irq"; 521 522 power-domains = <&gcc USB30_PRIM_GDSC>; 523 524 resets = <&gcc GCC_USB30_PRIM_BCR>; 525 526 usb@a600000 { 527 compatible = "snps,dwc3"; 528 reg = <0 0x0a600000 0 0xcd00>; 529 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 530 iommus = <&apps_smmu 0x740 0>; 531 snps,dis_u2_susphy_quirk; 532 snps,dis_enblslpm_quirk; 533 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 534 phy-names = "usb2-phy", "usb3-phy"; 535 }; 536 }; 537 }; 538