1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,msm8996-dwc3
17          - qcom,msm8998-dwc3
18          - qcom,sc7180-dwc3
19          - qcom,sc7280-dwc3
20          - qcom,sdm845-dwc3
21          - qcom,sdx55-dwc3
22          - qcom,sm8150-dwc3
23          - qcom,sm8250-dwc3
24          - qcom,sm8350-dwc3
25      - const: qcom,dwc3
26
27  reg:
28    description: Offset and length of register set for QSCRATCH wrapper
29    maxItems: 1
30
31  "#address-cells":
32    enum: [ 1, 2 ]
33
34  "#size-cells":
35    enum: [ 1, 2 ]
36
37  ranges: true
38
39  power-domains:
40    description: specifies a phandle to PM domain provider node
41    maxItems: 1
42
43  clocks:
44    description:
45      A list of phandle and clock-specifier pairs for the clocks
46      listed in clock-names.
47    items:
48      - description: System Config NOC clock.
49      - description: Master/Core clock, has to be >= 125 MHz
50          for SS operation and >= 60MHz for HS operation.
51      - description: System bus AXI clock.
52      - description: Mock utmi clock needed for ITP/SOF generation
53          in host mode. Its frequency should be 19.2MHz.
54      - description: Sleep clock, used for wakeup when
55          USB3 core goes into low power mode (U3).
56
57  clock-names:
58    items:
59      - const: cfg_noc
60      - const: core
61      - const: iface
62      - const: mock_utmi
63      - const: sleep
64
65  assigned-clocks:
66    items:
67      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
68      - description: Phandle and clock specifoer of MASTER_CLK.
69
70  assigned-clock-rates:
71    items:
72      - description: Must be 19.2MHz (19200000).
73      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
74  resets:
75    maxItems: 1
76
77  interconnects:
78    maxItems: 2
79
80  interconnect-names:
81    items:
82      - const: usb-ddr
83      - const: apps-usb
84
85  interrupts:
86    items:
87      - description: The interrupt that is asserted
88          when a wakeup event is received on USB2 bus.
89      - description: The interrupt that is asserted
90          when a wakeup event is received on USB3 bus.
91      - description: Wakeup event on DM line.
92      - description: Wakeup event on DP line.
93
94  interrupt-names:
95    items:
96      - const: hs_phy_irq
97      - const: ss_phy_irq
98      - const: dm_hs_phy_irq
99      - const: dp_hs_phy_irq
100
101  qcom,select-utmi-as-pipe-clk:
102    description:
103      If present, disable USB3 pipe_clk requirement.
104      Used when dwc3 operates without SSPHY and only
105      HS/FS/LS modes are supported.
106    type: boolean
107
108# Required child node:
109
110patternProperties:
111  "^usb@[0-9a-f]+$":
112    $ref: snps,dwc3.yaml#
113
114required:
115  - compatible
116  - reg
117  - "#address-cells"
118  - "#size-cells"
119  - ranges
120  - power-domains
121  - clocks
122  - clock-names
123  - interrupts
124  - interrupt-names
125
126additionalProperties: false
127
128examples:
129  - |
130    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
131    #include <dt-bindings/interrupt-controller/arm-gic.h>
132    #include <dt-bindings/interrupt-controller/irq.h>
133    soc {
134        #address-cells = <2>;
135        #size-cells = <2>;
136
137        usb@a6f8800 {
138            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
139            reg = <0 0x0a6f8800 0 0x400>;
140
141            #address-cells = <2>;
142            #size-cells = <2>;
143            ranges;
144            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
145                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
146                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
147                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
148                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
149            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
150                      "sleep";
151
152            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
153                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
154            assigned-clock-rates = <19200000>, <150000000>;
155
156            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
157                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
158                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
159                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
160            interrupt-names = "hs_phy_irq", "ss_phy_irq",
161                          "dm_hs_phy_irq", "dp_hs_phy_irq";
162
163            power-domains = <&gcc USB30_PRIM_GDSC>;
164
165            resets = <&gcc GCC_USB30_PRIM_BCR>;
166
167            usb@a600000 {
168                compatible = "snps,dwc3";
169                reg = <0 0x0a600000 0 0xcd00>;
170                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
171                iommus = <&apps_smmu 0x740 0>;
172                snps,dis_u2_susphy_quirk;
173                snps,dis_enblslpm_quirk;
174                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
175                phy-names = "usb2-phy", "usb3-phy";
176            };
177        };
178    };
179