1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,ipq4019-dwc3
17          - qcom,ipq6018-dwc3
18          - qcom,ipq8064-dwc3
19          - qcom,ipq8074-dwc3
20          - qcom,msm8953-dwc3
21          - qcom,msm8994-dwc3
22          - qcom,msm8996-dwc3
23          - qcom,msm8998-dwc3
24          - qcom,qcs404-dwc3
25          - qcom,sc7180-dwc3
26          - qcom,sc7280-dwc3
27          - qcom,sdm660-dwc3
28          - qcom,sdm845-dwc3
29          - qcom,sdx55-dwc3
30          - qcom,sdx65-dwc3
31          - qcom,sm4250-dwc3
32          - qcom,sm6115-dwc3
33          - qcom,sm6125-dwc3
34          - qcom,sm6350-dwc3
35          - qcom,sm8150-dwc3
36          - qcom,sm8250-dwc3
37          - qcom,sm8350-dwc3
38          - qcom,sm8450-dwc3
39      - const: qcom,dwc3
40
41  reg:
42    description: Offset and length of register set for QSCRATCH wrapper
43    maxItems: 1
44
45  "#address-cells":
46    enum: [ 1, 2 ]
47
48  "#size-cells":
49    enum: [ 1, 2 ]
50
51  ranges: true
52
53  power-domains:
54    description: specifies a phandle to PM domain provider node
55    maxItems: 1
56
57  clocks:
58    description: |
59      Several clocks are used, depending on the variant. Typical ones are::
60       - cfg_noc:: System Config NOC clock.
61       - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
62                60MHz for HS operation.
63       - iface:: System bus AXI clock.
64       - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
65                 power mode (U3).
66       - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
67                     mode. Its frequency should be 19.2MHz.
68    minItems: 1
69    maxItems: 6
70
71  clock-names:
72    minItems: 1
73    maxItems: 6
74
75  assigned-clocks:
76    items:
77      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
78      - description: Phandle and clock specifoer of MASTER_CLK.
79
80  assigned-clock-rates:
81    items:
82      - description: Must be 19.2MHz (19200000).
83      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
84  resets:
85    maxItems: 1
86
87  interconnects:
88    maxItems: 2
89
90  interconnect-names:
91    items:
92      - const: usb-ddr
93      - const: apps-usb
94
95  interrupts:
96    items:
97      - description: The interrupt that is asserted
98          when a wakeup event is received on USB2 bus.
99      - description: The interrupt that is asserted
100          when a wakeup event is received on USB3 bus.
101      - description: Wakeup event on DM line.
102      - description: Wakeup event on DP line.
103
104  interrupt-names:
105    items:
106      - const: hs_phy_irq
107      - const: ss_phy_irq
108      - const: dm_hs_phy_irq
109      - const: dp_hs_phy_irq
110
111  qcom,select-utmi-as-pipe-clk:
112    description:
113      If present, disable USB3 pipe_clk requirement.
114      Used when dwc3 operates without SSPHY and only
115      HS/FS/LS modes are supported.
116    type: boolean
117
118# Required child node:
119
120patternProperties:
121  "^usb@[0-9a-f]+$":
122    $ref: snps,dwc3.yaml#
123
124required:
125  - compatible
126  - reg
127  - "#address-cells"
128  - "#size-cells"
129  - ranges
130  - power-domains
131  - clocks
132  - clock-names
133  - interrupts
134  - interrupt-names
135
136allOf:
137  - if:
138      properties:
139        compatible:
140          contains:
141            enum:
142              - qcom,ipq4019-dwc3
143    then:
144      properties:
145        clocks:
146          maxItems: 3
147        clock-names:
148          items:
149            - const: core
150            - const: sleep
151            - const: mock_utmi
152
153  - if:
154      properties:
155        compatible:
156          contains:
157            enum:
158              - qcom,ipq8064-dwc3
159    then:
160      properties:
161        clocks:
162          items:
163            - description: Master/Core clock, has to be >= 125 MHz
164                for SS operation and >= 60MHz for HS operation.
165        clock-names:
166          items:
167            - const: core
168
169  - if:
170      properties:
171        compatible:
172          contains:
173            enum:
174              - qcom,msm8953-dwc3
175              - qcom,msm8996-dwc3
176              - qcom,msm8998-dwc3
177              - qcom,sc7180-dwc3
178              - qcom,sc7280-dwc3
179              - qcom,sdm845-dwc3
180              - qcom,sdx55-dwc3
181              - qcom,sm6350-dwc3
182    then:
183      properties:
184        clocks:
185          maxItems: 5
186        clock-names:
187          items:
188            - const: cfg_noc
189            - const: core
190            - const: iface
191            - const: sleep
192            - const: mock_utmi
193
194  - if:
195      properties:
196        compatible:
197          contains:
198            enum:
199              - qcom,ipq6018-dwc3
200    then:
201      properties:
202        clocks:
203          minItems: 3
204          maxItems: 4
205        clock-names:
206          oneOf:
207            - items:
208                - const: core
209                - const: sleep
210                - const: mock_utmi
211            - items:
212                - const: cfg_noc
213                - const: core
214                - const: sleep
215                - const: mock_utmi
216
217  - if:
218      properties:
219        compatible:
220          contains:
221            enum:
222              - qcom,ipq8074-dwc3
223    then:
224      properties:
225        clocks:
226          maxItems: 4
227        clock-names:
228          items:
229            - const: cfg_noc
230            - const: core
231            - const: sleep
232            - const: mock_utmi
233
234  - if:
235      properties:
236        compatible:
237          contains:
238            enum:
239              - qcom,msm8994-dwc3
240              - qcom,qcs404-dwc3
241    then:
242      properties:
243        clocks:
244          maxItems: 4
245        clock-names:
246          items:
247            - const: core
248            - const: iface
249            - const: sleep
250            - const: mock_utmi
251
252  - if:
253      properties:
254        compatible:
255          contains:
256            enum:
257              - qcom,sdm660-dwc3
258    then:
259      properties:
260        clocks:
261          minItems: 6
262        clock-names:
263          items:
264            - const: cfg_noc
265            - const: core
266            - const: iface
267            - const: sleep
268            - const: mock_utmi
269            - const: bus
270
271  - if:
272      properties:
273        compatible:
274          contains:
275            enum:
276              - qcom,sm6125-dwc3
277              - qcom,sm8150-dwc3
278              - qcom,sm8250-dwc3
279              - qcom,sm8450-dwc3
280    then:
281      properties:
282        clocks:
283          minItems: 6
284        clock-names:
285          items:
286            - const: cfg_noc
287            - const: core
288            - const: iface
289            - const: sleep
290            - const: mock_utmi
291            - const: xo
292
293  - if:
294      properties:
295        compatible:
296          contains:
297            enum:
298              - qcom,sm8350-dwc3
299    then:
300      properties:
301        clocks:
302          minItems: 5
303          maxItems: 6
304        clock-names:
305          minItems: 5
306          items:
307            - const: cfg_noc
308            - const: core
309            - const: iface
310            - const: sleep
311            - const: mock_utmi
312            - const: xo
313
314
315additionalProperties: false
316
317examples:
318  - |
319    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
320    #include <dt-bindings/interrupt-controller/arm-gic.h>
321    #include <dt-bindings/interrupt-controller/irq.h>
322    soc {
323        #address-cells = <2>;
324        #size-cells = <2>;
325
326        usb@a6f8800 {
327            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
328            reg = <0 0x0a6f8800 0 0x400>;
329
330            #address-cells = <2>;
331            #size-cells = <2>;
332            ranges;
333            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
334                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
335                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
336                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
337                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
338            clock-names = "cfg_noc",
339                          "core",
340                          "iface",
341                          "sleep",
342                          "mock_utmi";
343
344            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
345                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
346            assigned-clock-rates = <19200000>, <150000000>;
347
348            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
349                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
350                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
351                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
352            interrupt-names = "hs_phy_irq", "ss_phy_irq",
353                          "dm_hs_phy_irq", "dp_hs_phy_irq";
354
355            power-domains = <&gcc USB30_PRIM_GDSC>;
356
357            resets = <&gcc GCC_USB30_PRIM_BCR>;
358
359            usb@a600000 {
360                compatible = "snps,dwc3";
361                reg = <0 0x0a600000 0 0xcd00>;
362                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
363                iommus = <&apps_smmu 0x740 0>;
364                snps,dis_u2_susphy_quirk;
365                snps,dis_enblslpm_quirk;
366                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
367                phy-names = "usb2-phy", "usb3-phy";
368            };
369        };
370    };
371