1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq6018-dwc3 18 - qcom,ipq8064-dwc3 19 - qcom,ipq8074-dwc3 20 - qcom,msm8953-dwc3 21 - qcom,msm8994-dwc3 22 - qcom,msm8996-dwc3 23 - qcom,msm8998-dwc3 24 - qcom,qcs404-dwc3 25 - qcom,sc7180-dwc3 26 - qcom,sc7280-dwc3 27 - qcom,sc8280xp-dwc3 28 - qcom,sdm660-dwc3 29 - qcom,sdm845-dwc3 30 - qcom,sdx55-dwc3 31 - qcom,sdx65-dwc3 32 - qcom,sm4250-dwc3 33 - qcom,sm6115-dwc3 34 - qcom,sm6125-dwc3 35 - qcom,sm6350-dwc3 36 - qcom,sm8150-dwc3 37 - qcom,sm8250-dwc3 38 - qcom,sm8350-dwc3 39 - qcom,sm8450-dwc3 40 - const: qcom,dwc3 41 42 reg: 43 description: Offset and length of register set for QSCRATCH wrapper 44 maxItems: 1 45 46 "#address-cells": 47 enum: [ 1, 2 ] 48 49 "#size-cells": 50 enum: [ 1, 2 ] 51 52 ranges: true 53 54 power-domains: 55 description: specifies a phandle to PM domain provider node 56 maxItems: 1 57 58 clocks: 59 description: | 60 Several clocks are used, depending on the variant. Typical ones are:: 61 - cfg_noc:: System Config NOC clock. 62 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 63 60MHz for HS operation. 64 - iface:: System bus AXI clock. 65 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 66 power mode (U3). 67 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 68 mode. Its frequency should be 19.2MHz. 69 minItems: 1 70 maxItems: 9 71 72 clock-names: 73 minItems: 1 74 maxItems: 9 75 76 assigned-clocks: 77 items: 78 - description: Phandle and clock specifier of MOCK_UTMI_CLK. 79 - description: Phandle and clock specifoer of MASTER_CLK. 80 81 assigned-clock-rates: 82 items: 83 - description: Must be 19.2MHz (19200000). 84 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. 85 resets: 86 maxItems: 1 87 88 interconnects: 89 maxItems: 2 90 91 interconnect-names: 92 items: 93 - const: usb-ddr 94 - const: apps-usb 95 96 interrupts: 97 minItems: 1 98 maxItems: 4 99 100 interrupt-names: 101 minItems: 1 102 maxItems: 4 103 104 qcom,select-utmi-as-pipe-clk: 105 description: 106 If present, disable USB3 pipe_clk requirement. 107 Used when dwc3 operates without SSPHY and only 108 HS/FS/LS modes are supported. 109 type: boolean 110 111# Required child node: 112 113patternProperties: 114 "^usb@[0-9a-f]+$": 115 $ref: snps,dwc3.yaml# 116 117required: 118 - compatible 119 - reg 120 - "#address-cells" 121 - "#size-cells" 122 - ranges 123 - power-domains 124 - clocks 125 - clock-names 126 - interrupts 127 - interrupt-names 128 129allOf: 130 - if: 131 properties: 132 compatible: 133 contains: 134 enum: 135 - qcom,ipq4019-dwc3 136 then: 137 properties: 138 clocks: 139 maxItems: 3 140 clock-names: 141 items: 142 - const: core 143 - const: sleep 144 - const: mock_utmi 145 146 - if: 147 properties: 148 compatible: 149 contains: 150 enum: 151 - qcom,ipq8064-dwc3 152 then: 153 properties: 154 clocks: 155 items: 156 - description: Master/Core clock, has to be >= 125 MHz 157 for SS operation and >= 60MHz for HS operation. 158 clock-names: 159 items: 160 - const: core 161 162 - if: 163 properties: 164 compatible: 165 contains: 166 enum: 167 - qcom,msm8953-dwc3 168 - qcom,msm8996-dwc3 169 - qcom,msm8998-dwc3 170 - qcom,sc7180-dwc3 171 - qcom,sc7280-dwc3 172 - qcom,sdm845-dwc3 173 - qcom,sdx55-dwc3 174 - qcom,sm6350-dwc3 175 then: 176 properties: 177 clocks: 178 maxItems: 5 179 clock-names: 180 items: 181 - const: cfg_noc 182 - const: core 183 - const: iface 184 - const: sleep 185 - const: mock_utmi 186 187 - if: 188 properties: 189 compatible: 190 contains: 191 enum: 192 - qcom,ipq6018-dwc3 193 then: 194 properties: 195 clocks: 196 minItems: 3 197 maxItems: 4 198 clock-names: 199 oneOf: 200 - items: 201 - const: core 202 - const: sleep 203 - const: mock_utmi 204 - items: 205 - const: cfg_noc 206 - const: core 207 - const: sleep 208 - const: mock_utmi 209 210 - if: 211 properties: 212 compatible: 213 contains: 214 enum: 215 - qcom,ipq8074-dwc3 216 then: 217 properties: 218 clocks: 219 maxItems: 4 220 clock-names: 221 items: 222 - const: cfg_noc 223 - const: core 224 - const: sleep 225 - const: mock_utmi 226 227 - if: 228 properties: 229 compatible: 230 contains: 231 enum: 232 - qcom,msm8994-dwc3 233 - qcom,qcs404-dwc3 234 then: 235 properties: 236 clocks: 237 maxItems: 4 238 clock-names: 239 items: 240 - const: core 241 - const: iface 242 - const: sleep 243 - const: mock_utmi 244 245 - if: 246 properties: 247 compatible: 248 contains: 249 enum: 250 - qcom,sc8280xp-dwc3 251 then: 252 properties: 253 clocks: 254 maxItems: 9 255 clock-names: 256 items: 257 - const: cfg_noc 258 - const: core 259 - const: iface 260 - const: sleep 261 - const: mock_utmi 262 - const: noc_aggr 263 - const: noc_aggr_north 264 - const: noc_aggr_south 265 - const: noc_sys 266 267 - if: 268 properties: 269 compatible: 270 contains: 271 enum: 272 - qcom,sdm660-dwc3 273 then: 274 properties: 275 clocks: 276 minItems: 6 277 clock-names: 278 items: 279 - const: cfg_noc 280 - const: core 281 - const: iface 282 - const: sleep 283 - const: mock_utmi 284 - const: bus 285 286 - if: 287 properties: 288 compatible: 289 contains: 290 enum: 291 - qcom,sm6125-dwc3 292 - qcom,sm8150-dwc3 293 - qcom,sm8250-dwc3 294 - qcom,sm8450-dwc3 295 then: 296 properties: 297 clocks: 298 minItems: 6 299 clock-names: 300 items: 301 - const: cfg_noc 302 - const: core 303 - const: iface 304 - const: sleep 305 - const: mock_utmi 306 - const: xo 307 308 - if: 309 properties: 310 compatible: 311 contains: 312 enum: 313 - qcom,sm8350-dwc3 314 then: 315 properties: 316 clocks: 317 minItems: 5 318 maxItems: 6 319 clock-names: 320 minItems: 5 321 items: 322 - const: cfg_noc 323 - const: core 324 - const: iface 325 - const: sleep 326 - const: mock_utmi 327 - const: xo 328 329 - if: 330 properties: 331 compatible: 332 contains: 333 enum: 334 - qcom,ipq4019-dwc3 335 - qcom,ipq6018-dwc3 336 - qcom,ipq8064-dwc3 337 - qcom,ipq8074-dwc3 338 - qcom,msm8994-dwc3 339 - qcom,qcs404-dwc3 340 - qcom,sc7180-dwc3 341 - qcom,sdm845-dwc3 342 - qcom,sdx55-dwc3 343 - qcom,sdx65-dwc3 344 - qcom,sm4250-dwc3 345 - qcom,sm6115-dwc3 346 - qcom,sm6125-dwc3 347 - qcom,sm6350-dwc3 348 - qcom,sm8150-dwc3 349 - qcom,sm8250-dwc3 350 - qcom,sm8350-dwc3 351 - qcom,sm8450-dwc3 352 then: 353 properties: 354 interrupts: 355 items: 356 - description: The interrupt that is asserted 357 when a wakeup event is received on USB2 bus. 358 - description: The interrupt that is asserted 359 when a wakeup event is received on USB3 bus. 360 - description: Wakeup event on DM line. 361 - description: Wakeup event on DP line. 362 interrupt-names: 363 items: 364 - const: hs_phy_irq 365 - const: ss_phy_irq 366 - const: dm_hs_phy_irq 367 - const: dp_hs_phy_irq 368 369 - if: 370 properties: 371 compatible: 372 contains: 373 enum: 374 - qcom,msm8953-dwc3 375 - qcom,msm8996-dwc3 376 - qcom,msm8998-dwc3 377 then: 378 properties: 379 interrupts: 380 maxItems: 2 381 interrupt-names: 382 items: 383 - const: hs_phy_irq 384 - const: ss_phy_irq 385 386 - if: 387 properties: 388 compatible: 389 contains: 390 enum: 391 - qcom,sdm660-dwc3 392 then: 393 properties: 394 interrupts: 395 minItems: 1 396 maxItems: 2 397 interrupt-names: 398 minItems: 1 399 items: 400 - const: hs_phy_irq 401 - const: ss_phy_irq 402 403 - if: 404 properties: 405 compatible: 406 contains: 407 enum: 408 - qcom,sc7280-dwc3 409 then: 410 properties: 411 interrupts: 412 minItems: 3 413 maxItems: 4 414 interrupt-names: 415 minItems: 3 416 items: 417 - const: hs_phy_irq 418 - const: dp_hs_phy_irq 419 - const: dm_hs_phy_irq 420 - const: ss_phy_irq 421 422 - if: 423 properties: 424 compatible: 425 contains: 426 enum: 427 - qcom,sc8280xp-dwc3 428 then: 429 properties: 430 interrupts: 431 maxItems: 4 432 interrupt-names: 433 items: 434 - const: pwr_event 435 - const: dp_hs_phy_irq 436 - const: dm_hs_phy_irq 437 - const: ss_phy_irq 438 439additionalProperties: false 440 441examples: 442 - | 443 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 444 #include <dt-bindings/interrupt-controller/arm-gic.h> 445 #include <dt-bindings/interrupt-controller/irq.h> 446 soc { 447 #address-cells = <2>; 448 #size-cells = <2>; 449 450 usb@a6f8800 { 451 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 452 reg = <0 0x0a6f8800 0 0x400>; 453 454 #address-cells = <2>; 455 #size-cells = <2>; 456 ranges; 457 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 458 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 459 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 460 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 461 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 462 clock-names = "cfg_noc", 463 "core", 464 "iface", 465 "sleep", 466 "mock_utmi"; 467 468 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 469 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 470 assigned-clock-rates = <19200000>, <150000000>; 471 472 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 476 interrupt-names = "hs_phy_irq", "ss_phy_irq", 477 "dm_hs_phy_irq", "dp_hs_phy_irq"; 478 479 power-domains = <&gcc USB30_PRIM_GDSC>; 480 481 resets = <&gcc GCC_USB30_PRIM_BCR>; 482 483 usb@a600000 { 484 compatible = "snps,dwc3"; 485 reg = <0 0x0a600000 0 0xcd00>; 486 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 487 iommus = <&apps_smmu 0x740 0>; 488 snps,dis_u2_susphy_quirk; 489 snps,dis_enblslpm_quirk; 490 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 491 phy-names = "usb2-phy", "usb3-phy"; 492 }; 493 }; 494 }; 495