1OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
2
3OMAP MUSB GLUE
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7   multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9   MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12   interface between the controller and the phy. It should be "0" or "1"
13   specifying ULPI and UTMI respectively.
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
15   represents PERIPHERAL.
16 - power : Should be "50". This signifies the controller can supply up to
17   100mA when operating in host mode.
18 - usb-phy : the phandle for the PHY device
19 - phys : the phandle for the PHY device (used by generic PHY framework)
20 - phy-names : the names of the PHY corresponding to the PHYs present in the
21   *phy* phandle.
22
23Optional properties:
24 - ctrl-module : phandle of the control module this glue uses to write to
25   mailbox
26
27SOC specific device node entry
28usb_otg_hs: usb_otg_hs@4a0ab000 {
29	compatible = "ti,omap4-musb";
30	ti,hwmods = "usb_otg_hs";
31	multipoint = <1>;
32	num-eps = <16>;
33	ram-bits = <12>;
34	ctrl-module = <&omap_control_usb>;
35	phys = <&usb2_phy>;
36	phy-names = "usb2-phy";
37};
38
39Board specific device node entry
40&usb_otg_hs {
41	interface-type = <1>;
42	mode = <3>;
43	power = <50>;
44};
45
46OMAP DWC3 GLUE
47 - compatible : Should be "ti,dwc3"
48 - ti,hwmods : Should be "usb_otg_ss"
49 - reg : Address and length of the register set for the device.
50 - interrupts : The irq number of this device that is used to interrupt the
51   MPU
52 - #address-cells, #size-cells : Must be present if the device has sub-nodes
53 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
54   It should be set to "1" for HW mode and "2" for SW mode.
55 - ranges: the child address space are mapped 1:1 onto the parent address space
56
57Optional Properties:
58 - extcon : phandle for the extcon device omap dwc3 uses to detect
59   connect/disconnect events.
60 - vbus-supply : phandle to the regulator device tree node if needed.
61
62Sub-nodes:
63The dwc3 core should be added as subnode to omap dwc3 glue.
64- dwc3 :
65   The binding details of dwc3 can be found in:
66   Documentation/devicetree/bindings/usb/dwc3.txt
67
68omap_dwc3 {
69	compatible = "ti,dwc3";
70	ti,hwmods = "usb_otg_ss";
71	reg = <0x4a020000 0x1ff>;
72	interrupts = <0 93 4>;
73	#address-cells = <1>;
74	#size-cells = <1>;
75	utmi-mode = <2>;
76	ranges;
77};
78
79OMAP CONTROL USB
80
81Required properties:
82 - compatible: Should be one of
83 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
84 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
85			e.g. USB2_PHY on OMAP5.
86 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
87			e.g. USB3 PHY and SATA PHY on OMAP5.
88 "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
89			DRA7 platform.
90 - reg : Address and length of the register set for the device. It contains
91   the address of "otghs_control" for control-phy-otghs or "power" register
92   for other types.
93 - reg-names: should be "otghs_control" control-phy-otghs and "power" for
94   other types.
95
96omap_control_usb: omap-control-usb@4a002300 {
97	compatible = "ti,control-phy-otghs";
98	reg = <0x4a00233c 0x4>;
99	reg-names = "otghs_control";
100};
101