1OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
2
3OMAP MUSB GLUE
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - ti,has-mailbox : to specify that omap uses an external mailbox
7   (in control module) to communicate with the musb core during device connect
8   and disconnect.
9 - multipoint : Should be "1" indicating the musb controller supports
10   multipoint. This is a MUSB configuration-specific setting.
11 - num-eps : Specifies the number of endpoints. This is also a
12   MUSB configuration-specific setting. Should be set to "16"
13 - ram-bits : Specifies the ram address size. Should be set to "12"
14 - interface-type : This is a board specific setting to describe the type of
15   interface between the controller and the phy. It should be "0" or "1"
16   specifying ULPI and UTMI respectively.
17 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
18   represents PERIPHERAL.
19 - power : Should be "50". This signifies the controller can supply up to
20   100mA when operating in host mode.
21 - usb-phy : the phandle for the PHY device
22
23Optional properties:
24 - ctrl-module : phandle of the control module this glue uses to write to
25   mailbox
26
27SOC specific device node entry
28usb_otg_hs: usb_otg_hs@4a0ab000 {
29	compatible = "ti,omap4-musb";
30	ti,hwmods = "usb_otg_hs";
31	ti,has-mailbox;
32	multipoint = <1>;
33	num-eps = <16>;
34	ram-bits = <12>;
35	ctrl-module = <&omap_control_usb>;
36};
37
38Board specific device node entry
39&usb_otg_hs {
40	interface-type = <1>;
41	mode = <3>;
42	power = <50>;
43};
44
45OMAP DWC3 GLUE
46 - compatible : Should be "ti,dwc3"
47 - ti,hwmods : Should be "usb_otg_ss"
48 - reg : Address and length of the register set for the device.
49 - interrupts : The irq number of this device that is used to interrupt the
50   MPU
51 - #address-cells, #size-cells : Must be present if the device has sub-nodes
52 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
53   It should be set to "1" for HW mode and "2" for SW mode.
54 - ranges: the child address space are mapped 1:1 onto the parent address space
55
56Optional Properties:
57 - extcon : phandle for the extcon device omap dwc3 uses to detect
58   connect/disconnect events.
59 - vbus-supply : phandle to the regulator device tree node if needed.
60
61Sub-nodes:
62The dwc3 core should be added as subnode to omap dwc3 glue.
63- dwc3 :
64   The binding details of dwc3 can be found in:
65   Documentation/devicetree/bindings/usb/dwc3.txt
66
67omap_dwc3 {
68	compatible = "ti,dwc3";
69	ti,hwmods = "usb_otg_ss";
70	reg = <0x4a020000 0x1ff>;
71	interrupts = <0 93 4>;
72	#address-cells = <1>;
73	#size-cells = <1>;
74	utmi-mode = <2>;
75	ranges;
76};
77
78OMAP CONTROL USB
79
80Required properties:
81 - compatible: Should be "ti,omap-control-usb"
82 - reg : Address and length of the register set for the device. It contains
83   the address of "control_dev_conf" and "otghs_control" or "phy_power_usb"
84   depending upon omap4 or omap5.
85 - reg-names: The names of the register addresses corresponding to the registers
86   filled in "reg".
87 - ti,type: This is used to differentiate whether the control module has
88   usb mailbox or usb3 phy power. omap4 has usb mailbox in control module to
89   notify events to the musb core and omap5 has usb3 phy power register to
90   power on usb3 phy. Should be "1" if it has mailbox and "2" if it has usb3
91   phy power.
92
93omap_control_usb: omap-control-usb@4a002300 {
94	compatible = "ti,omap-control-usb";
95	reg = <0x4a002300 0x4>,
96	      <0x4a00233c 0x4>;
97	reg-names = "control_dev_conf", "otghs_control";
98	ti,type = <1>;
99};
100