1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: USB2 ChipIdea USB controller
8
9maintainers:
10  - Xu Yang <xu.yang_2@nxp.com>
11  - Peng Fan <peng.fan@nxp.com>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - chipidea,usb2
18          - lsi,zevio-usb
19          - nvidia,tegra20-ehci
20          - nvidia,tegra20-udc
21          - nvidia,tegra30-ehci
22          - nvidia,tegra30-udc
23          - nvidia,tegra114-udc
24          - nvidia,tegra124-udc
25          - qcom,ci-hdrc
26      - items:
27          - enum:
28              - nvidia,tegra114-ehci
29              - nvidia,tegra124-ehci
30              - nvidia,tegra210-ehci
31          - const: nvidia,tegra30-ehci
32      - items:
33          - enum:
34              - fsl,imx23-usb
35              - fsl,imx25-usb
36              - fsl,imx28-usb
37              - fsl,imx50-usb
38              - fsl,imx51-usb
39              - fsl,imx53-usb
40              - fsl,imx6q-usb
41              - fsl,imx6sl-usb
42              - fsl,imx6sx-usb
43              - fsl,imx6ul-usb
44              - fsl,imx7d-usb
45              - fsl,vf610-usb
46          - const: fsl,imx27-usb
47      - items:
48          - enum:
49              - fsl,imx8dxl-usb
50              - fsl,imx8ulp-usb
51          - const: fsl,imx7ulp-usb
52          - const: fsl,imx6ul-usb
53      - items:
54          - enum:
55              - fsl,imx8mm-usb
56              - fsl,imx8mn-usb
57          - const: fsl,imx7d-usb
58          - const: fsl,imx27-usb
59      - items:
60          - enum:
61              - fsl,imx6sll-usb
62              - fsl,imx7ulp-usb
63          - const: fsl,imx6ul-usb
64          - const: fsl,imx27-usb
65      - items:
66          - const: xlnx,zynq-usb-2.20a
67          - const: chipidea,usb2
68
69  reg:
70    minItems: 1
71    maxItems: 2
72
73  interrupts:
74    minItems: 1
75    maxItems: 2
76
77  clocks:
78    minItems: 1
79    maxItems: 2
80
81  clock-names:
82    minItems: 1
83    maxItems: 2
84
85  dr_mode: true
86
87  power-domains:
88    maxItems: 1
89
90  resets:
91    maxItems: 1
92
93  reset-names:
94    maxItems: 1
95
96  "#reset-cells":
97    const: 1
98
99  phy_type: true
100
101  itc-setting:
102    description:
103      interrupt threshold control register control, the setting should be
104      aligned with ITC bits at register USBCMD.
105    $ref: /schemas/types.yaml#/definitions/uint32
106
107  ahb-burst-config:
108    description:
109      it is vendor dependent, the required value should be aligned with
110      AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is
111      used to change AHB burst configuration, check the chipidea spec for
112      meaning of each value. If this property is not existed, it will use
113      the reset value.
114    $ref: /schemas/types.yaml#/definitions/uint32
115    minimum: 0x0
116    maximum: 0x7
117
118  tx-burst-size-dword:
119    description:
120      it is vendor dependent, the tx burst size in dword (4 bytes), This
121      register represents the maximum length of a the burst in 32-bit
122      words while moving data from system memory to the USB bus, the value
123      of this property will only take effect if property "ahb-burst-config"
124      is set to 0, if this property is missing the reset default of the
125      hardware implementation will be used.
126    $ref: /schemas/types.yaml#/definitions/uint32
127    minimum: 0x0
128    maximum: 0x20
129
130  rx-burst-size-dword:
131    description:
132      it is vendor dependent, the rx burst size in dword (4 bytes), This
133      register represents the maximum length of a the burst in 32-bit words
134      while moving data from the USB bus to system memory, the value of
135      this property will only take effect if property "ahb-burst-config"
136      is set to 0, if this property is missing the reset default of the
137      hardware implementation will be used.
138    $ref: /schemas/types.yaml#/definitions/uint32
139    minimum: 0x0
140    maximum: 0x20
141
142  extcon:
143    description:
144      Phandles to external connector devices. First phandle should point
145      to external connector, which provide "USB" cable events, the second
146      should point to external connector device, which provide "USB-HOST"
147      cable events. If one of the external connector devices is not
148      required, empty <0> phandle should be specified.
149    $ref: /schemas/types.yaml#/definitions/phandle-array
150    minItems: 1
151    items:
152      - description: vbus extcon
153      - description: id extcon
154
155  phy-clkgate-delay-us:
156    description:
157      The delay time (us) between putting the PHY into low power mode and
158      gating the PHY clock.
159
160  non-zero-ttctrl-ttha:
161    description:
162      After setting this property, the value of register ttctrl.ttha
163      will be 0x7f; if not, the value will be 0x0, this is the default
164      value. It needs to be very carefully for setting this property, it
165      is recommended that consult with your IC engineer before setting
166      this value.  On the most of chipidea platforms, the "usage_tt" flag
167      at RTL is 0, so this property only affects siTD.
168
169      If this property is not set, the max packet size is 1023 bytes, and
170      if the total of packet size for pervious transactions are more than
171      256 bytes, it can't accept any transactions within this frame. The
172      use case is single transaction, but higher frame rate.
173
174      If this property is set, the max packet size is 188 bytes, it can
175      handle more transactions than above case, it can accept transactions
176      until it considers the left room size within frame is less than 188
177      bytes, software needs to make sure it does not send more than 90%
178      maximum_periodic_data_per_frame. The use case is multiple
179      transactions, but less frame rate.
180    type: boolean
181
182  mux-controls:
183    description:
184      The mux control for toggling host/device output of this controller.
185      It's expected that a mux state of 0 indicates device mode and a mux
186      state of 1 indicates host mode.
187    maxItems: 1
188
189  mux-control-names:
190    const: usb_switch
191
192  operating-points-v2:
193    description: A phandle to the OPP table containing the performance states.
194    $ref: /schemas/types.yaml#/definitions/phandle
195
196  pinctrl-names:
197    description:
198      Names for optional pin modes in "default", "host", "device".
199      In case of HSIC-mode, "idle" and "active" pin modes are mandatory.
200      In this case, the "idle" state needs to pull down the data and
201      strobe pin and the "active" state needs to pull up the strobe pin.
202    oneOf:
203      - items:
204          - const: idle
205          - const: active
206      - items:
207          - const: default
208          - enum:
209              - host
210              - device
211      - items:
212          - const: default
213
214  pinctrl-0:
215    maxItems: 1
216
217  pinctrl-1:
218    maxItems: 1
219
220  phys:
221    maxItems: 1
222
223  phy-names:
224    const: usb-phy
225
226  phy-select:
227    description:
228      Phandler of TCSR node with two argument that indicate register
229      offset, and phy index
230    $ref: /schemas/types.yaml#/definitions/phandle-array
231    items:
232      - description: phandle to TCSR node
233      - description: register offset
234      - description: phy index
235
236  vbus-supply:
237    description: reference to the VBUS regulator.
238
239  fsl,usbmisc:
240    description:
241      Phandler of non-core register device, with one argument that
242      indicate usb controller index
243    $ref: /schemas/types.yaml#/definitions/phandle-array
244    items:
245      - items:
246          - description: phandle to usbmisc node
247          - description: index of usb controller
248
249  fsl,anatop:
250    description: phandle for the anatop node.
251    $ref: /schemas/types.yaml#/definitions/phandle
252
253  disable-over-current:
254    type: boolean
255    description: disable over current detect
256
257  over-current-active-low:
258    type: boolean
259    description: over current signal polarity is active low
260
261  over-current-active-high:
262    type: boolean
263    description:
264      Over current signal polarity is active high. It's recommended to
265      specify the over current polarity.
266
267  power-active-high:
268    type: boolean
269    description: power signal polarity is active high
270
271  external-vbus-divider:
272    type: boolean
273    description: enables off-chip resistor divider for Vbus
274
275  samsung,picophy-pre-emp-curr-control:
276    description:
277      HS Transmitter Pre-Emphasis Current Control. This signal controls
278      the amount of current sourced to the USB_OTG*_DP and USB_OTG*_DN
279      pins after a J-to-K or K-to-J transition. The range is from 0x0 to
280      0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0
281      bits of USBNC_n_PHY_CFG1.
282    $ref: /schemas/types.yaml#/definitions/uint32
283    minimum: 0x0
284    maximum: 0x3
285
286  samsung,picophy-dc-vol-level-adjust:
287    description:
288      HS DC Voltage Level Adjustment. Adjust the high-speed transmitter DC
289      level voltage. The range is from 0x0 to 0xf, the default value is
290      0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
291    $ref: /schemas/types.yaml#/definitions/uint32
292    minimum: 0x0
293    maximum: 0xf
294
295  usb-phy:
296    description: phandle for the PHY device. Use "phys" instead.
297    $ref: /schemas/types.yaml#/definitions/phandle
298    deprecated: true
299
300  fsl,usbphy:
301    description: phandle of usb phy that connects to the port. Use "phys" instead.
302    $ref: /schemas/types.yaml#/definitions/phandle
303    deprecated: true
304
305  nvidia,phy:
306    description: phandle of usb phy that connects to the port. Use "phys" instead.
307    $ref: /schemas/types.yaml#/definitions/phandle
308    deprecated: true
309
310  nvidia,needs-double-reset:
311    description: Indicates double reset or not.
312    type: boolean
313    deprecated: true
314
315  port:
316    description:
317      Any connector to the data bus of this controller should be modelled
318      using the OF graph bindings specified, if the "usb-role-switch"
319      property is used.
320    $ref: /schemas/graph.yaml#/properties/port
321
322  reset-gpios:
323    maxItems: 1
324
325  ulpi:
326    type: object
327    additionalProperties: false
328    patternProperties:
329      "^phy(-[0-9])?$":
330        description: The phy child node for Qcom chips.
331        type: object
332        $ref: /schemas/phy/qcom,usb-hs-phy.yaml
333
334dependencies:
335  port: [ usb-role-switch ]
336  mux-controls: [ mux-control-names ]
337
338required:
339  - compatible
340  - reg
341  - interrupts
342
343allOf:
344  - $ref: usb-hcd.yaml#
345  - $ref: usb-drd.yaml#
346  - if:
347      properties:
348        phy_type:
349          const: hsic
350      required:
351        - phy_type
352    then:
353      properties:
354        pinctrl-names:
355          items:
356            - const: idle
357            - const: active
358    else:
359      properties:
360        pinctrl-names:
361          minItems: 1
362          maxItems: 2
363          oneOf:
364            - items:
365                - const: default
366                - enum:
367                    - host
368                    - device
369            - items:
370                - const: default
371  - if:
372      properties:
373        compatible:
374          contains:
375            enum:
376              - chipidea,usb2
377              - lsi,zevio-usb
378              - nvidia,tegra20-udc
379              - nvidia,tegra30-udc
380              - nvidia,tegra114-udc
381              - nvidia,tegra124-udc
382              - qcom,ci-hdrc
383              - xlnx,zynq-usb-2.20a
384    then:
385      properties:
386        fsl,usbmisc: false
387        disable-over-current: false
388        over-current-active-low: false
389        over-current-active-high: false
390        power-active-high: false
391        external-vbus-divider: false
392        samsung,picophy-pre-emp-curr-control: false
393        samsung,picophy-dc-vol-level-adjust: false
394
395unevaluatedProperties: false
396
397examples:
398  - |
399    #include <dt-bindings/interrupt-controller/arm-gic.h>
400    #include <dt-bindings/clock/berlin2.h>
401
402    usb@f7ed0000 {
403        compatible = "chipidea,usb2";
404        reg = <0xf7ed0000 0x10000>;
405        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
406        clocks = <&chip CLKID_USB0>;
407        phys = <&usb_phy0>;
408        phy-names = "usb-phy";
409        vbus-supply = <&reg_usb0_vbus>;
410        itc-setting = <0x4>; /* 4 micro-frames */
411         /* Incremental burst of unspecified length */
412        ahb-burst-config = <0x0>;
413        tx-burst-size-dword = <0x10>; /* 64 bytes */
414        rx-burst-size-dword = <0x10>;
415        extcon = <0>, <&usb_id>;
416        phy-clkgate-delay-us = <400>;
417        mux-controls = <&usb_switch>;
418        mux-control-names = "usb_switch";
419    };
420
421  # Example for HSIC:
422  - |
423    #include <dt-bindings/interrupt-controller/arm-gic.h>
424    #include <dt-bindings/clock/imx6qdl-clock.h>
425
426    usb@2184400 {
427        compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
428        reg = <0x02184400 0x200>;
429        interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
430        clocks = <&clks IMX6QDL_CLK_USBOH3>;
431        fsl,usbphy = <&usbphynop1>;
432        fsl,usbmisc = <&usbmisc 2>;
433        phy_type = "hsic";
434        dr_mode = "host";
435        ahb-burst-config = <0x0>;
436        tx-burst-size-dword = <0x10>;
437        rx-burst-size-dword = <0x10>;
438        pinctrl-names = "idle", "active";
439        pinctrl-0 = <&pinctrl_usbh2_idle>;
440        pinctrl-1 = <&pinctrl_usbh2_active>;
441        #address-cells = <1>;
442        #size-cells = <0>;
443
444        ethernet@1 {
445            compatible = "usb424,9730";
446            reg = <1>;
447        };
448    };
449
450...
451