1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence USBSS-DRD controller bindings 8 9maintainers: 10 - Pawel Laszczak <pawell@cadence.com> 11 12properties: 13 compatible: 14 const: cdns,usb3 15 16 reg: 17 items: 18 - description: OTG controller registers 19 - description: XHCI Host controller registers 20 - description: DEVICE controller registers 21 22 reg-names: 23 items: 24 - const: otg 25 - const: xhci 26 - const: dev 27 28 interrupts: 29 items: 30 - description: OTG/DRD controller interrupt 31 - description: XHCI host controller interrupt 32 - description: Device controller interrupt 33 34 interrupt-names: 35 items: 36 - const: host 37 - const: peripheral 38 - const: otg 39 40 dr_mode: 41 enum: [host, otg, peripheral] 42 43 maximum-speed: 44 enum: [super-speed, high-speed, full-speed] 45 46 phys: 47 minItems: 1 48 maxItems: 2 49 50 phy-names: 51 minItems: 1 52 maxItems: 2 53 items: 54 anyOf: 55 - const: cdns3,usb2-phy 56 - const: cdns3,usb3-phy 57 58 cdns,on-chip-buff-size: 59 description: 60 size of memory intended as internal memory for endpoints 61 buffers expressed in KB 62 $ref: /schemas/types.yaml#/definitions/uint32 63 64 cdns,phyrst-a-enable: 65 description: Enable resetting of PHY if Rx fail is detected 66 type: boolean 67 68required: 69 - compatible 70 - reg 71 - reg-names 72 - interrupts 73 74additionalProperties: false 75 76examples: 77 - | 78 #include <dt-bindings/interrupt-controller/arm-gic.h> 79 bus { 80 #address-cells = <2>; 81 #size-cells = <2>; 82 83 usb@6000000 { 84 compatible = "cdns,usb3"; 85 reg = <0x00 0x6000000 0x00 0x10000>, 86 <0x00 0x6010000 0x00 0x10000>, 87 <0x00 0x6020000 0x00 0x10000>; 88 reg-names = "otg", "xhci", "dev"; 89 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 92 interrupt-names = "host", "peripheral", "otg"; 93 maximum-speed = "super-speed"; 94 dr_mode = "otg"; 95 }; 96 }; 97