1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI J721e UFS Host Controller Glue Driver
8
9maintainers:
10  - Vignesh Raghavendra <vigneshr@ti.com>
11
12properties:
13  compatible:
14    items:
15      - const: ti,j721e-ufs
16
17  reg:
18    maxItems: 1
19    description: address of TI UFS glue registers
20
21  clocks:
22    maxItems: 1
23    description: phandle to the M-PHY clock
24
25  power-domains:
26    maxItems: 1
27
28  assigned-clocks:
29    maxItems: 1
30
31  assigned-clock-parents:
32    maxItems: 1
33
34  "#address-cells":
35    const: 2
36
37  "#size-cells":
38    const: 2
39
40  ranges: true
41
42required:
43  - compatible
44  - reg
45  - clocks
46  - power-domains
47
48patternProperties:
49  "^ufs@[0-9a-f]+$":
50    $ref: cdns,ufshc.yaml
51    description: |
52      Cadence UFS controller node must be the child node.
53    unevaluatedProperties: false
54
55additionalProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/interrupt-controller/irq.h>
60    #include <dt-bindings/interrupt-controller/arm-gic.h>
61
62    bus {
63        #address-cells = <2>;
64        #size-cells = <2>;
65
66        ufs-wrapper@4e80000 {
67            compatible = "ti,j721e-ufs";
68            reg = <0x0 0x4e80000 0x0 0x100>;
69            power-domains = <&k3_pds 277>;
70            clocks = <&k3_clks 277 1>;
71            assigned-clocks = <&k3_clks 277 1>;
72            assigned-clock-parents = <&k3_clks 277 4>;
73
74            ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
75            #address-cells = <2>;
76            #size-cells = <2>;
77
78            ufs@4000 {
79                compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
80                reg = <0x0 0x4000 0x0 0x10000>;
81                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
82                freq-table-hz = <19200000 19200000>;
83                power-domains = <&k3_pds 277>;
84                clocks = <&k3_clks 277 1>;
85                assigned-clocks = <&k3_clks 277 1>;
86                assigned-clock-parents = <&k3_clks 277 4>;
87                clock-names = "core_clk";
88            };
89        };
90    };
91