1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series UFS host controller Device Tree Bindings
8
9maintainers:
10  - Alim Akhtar <alim.akhtar@samsung.com>
11
12description: |
13  Each Samsung UFS host controller instance should have its own node.
14  This binding define Samsung specific binding other then what is used
15  in the common ufshcd bindings
16  [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
17
18properties:
19
20  compatible:
21    enum:
22      - samsung,exynos7-ufs
23      - samsung,exynosautov9-ufs
24      - samsung,exynosautov9-ufs-vh
25
26  reg:
27    items:
28      - description: HCI register
29      - description: vendor specific register
30      - description: unipro register
31      - description: UFS protector register
32
33  reg-names:
34    items:
35      - const: hci
36      - const: vs_hci
37      - const: unipro
38      - const: ufsp
39
40  clocks:
41    items:
42      - description: ufs link core clock
43      - description: unipro main clock
44
45  clock-names:
46    items:
47      - const: core_clk
48      - const: sclk_unipro_main
49
50  interrupts:
51    maxItems: 1
52
53  phys:
54    maxItems: 1
55
56  phy-names:
57    const: ufs-phy
58
59  samsung,sysreg:
60    $ref: '/schemas/types.yaml#/definitions/phandle-array'
61    description: Should be phandle/offset pair. The phandle to the syscon node
62                 which indicates the FSYSx sysreg interface and the offset of
63                 the control register for UFS io coherency setting.
64
65  dma-coherent: true
66
67required:
68  - compatible
69  - reg
70  - interrupts
71  - phys
72  - phy-names
73  - clocks
74  - clock-names
75
76additionalProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/clock/exynos7-clk.h>
82
83    ufs: ufs@15570000 {
84       compatible = "samsung,exynos7-ufs";
85       reg = <0x15570000 0x100>,
86             <0x15570100 0x100>,
87             <0x15571000 0x200>,
88             <0x15572000 0x300>;
89       reg-names = "hci", "vs_hci", "unipro", "ufsp";
90       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
91       clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
92                <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
93       clock-names = "core_clk", "sclk_unipro_main";
94       pinctrl-names = "default";
95       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
96       phys = <&ufs_phy>;
97       phy-names = "ufs-phy";
98    };
99...
100