1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sc8280xp-ufshc
30          - qcom,sdm845-ufshc
31          - qcom,sm6350-ufshc
32          - qcom,sm8150-ufshc
33          - qcom,sm8250-ufshc
34          - qcom,sm8350-ufshc
35          - qcom,sm8450-ufshc
36      - const: qcom,ufshc
37      - const: jedec,ufs-2.0
38
39  clocks:
40    minItems: 8
41    maxItems: 11
42
43  clock-names:
44    minItems: 8
45    maxItems: 11
46
47  interconnects:
48    minItems: 2
49    maxItems: 2
50
51  interconnect-names:
52    items:
53      - const: ufs-ddr
54      - const: cpu-ufs
55
56  iommus:
57    minItems: 1
58    maxItems: 2
59
60  phys:
61    maxItems: 1
62
63  phy-names:
64    items:
65      - const: ufsphy
66
67  power-domains:
68    maxItems: 1
69
70  reg:
71    minItems: 1
72    maxItems: 2
73
74  required-opps:
75    maxItems: 1
76
77  resets:
78    maxItems: 1
79
80  '#reset-cells':
81    const: 1
82
83  reset-names:
84    items:
85      - const: rst
86
87  reset-gpios:
88    maxItems: 1
89    description:
90      GPIO connected to the RESET pin of the UFS memory device.
91
92required:
93  - compatible
94  - reg
95
96allOf:
97  - $ref: ufs-common.yaml
98
99  - if:
100      properties:
101        compatible:
102          contains:
103            enum:
104              - qcom,msm8998-ufshc
105              - qcom,sc8280xp-ufshc
106              - qcom,sm8250-ufshc
107              - qcom,sm8350-ufshc
108              - qcom,sm8450-ufshc
109    then:
110      properties:
111        clocks:
112          minItems: 8
113          maxItems: 8
114        clock-names:
115          items:
116            - const: core_clk
117            - const: bus_aggr_clk
118            - const: iface_clk
119            - const: core_clk_unipro
120            - const: ref_clk
121            - const: tx_lane0_sync_clk
122            - const: rx_lane0_sync_clk
123            - const: rx_lane1_sync_clk
124        reg:
125          minItems: 1
126          maxItems: 1
127
128  - if:
129      properties:
130        compatible:
131          contains:
132            enum:
133              - qcom,sdm845-ufshc
134              - qcom,sm6350-ufshc
135              - qcom,sm8150-ufshc
136    then:
137      properties:
138        clocks:
139          minItems: 9
140          maxItems: 9
141        clock-names:
142          items:
143            - const: core_clk
144            - const: bus_aggr_clk
145            - const: iface_clk
146            - const: core_clk_unipro
147            - const: ref_clk
148            - const: tx_lane0_sync_clk
149            - const: rx_lane0_sync_clk
150            - const: rx_lane1_sync_clk
151            - const: ice_core_clk
152        reg:
153          minItems: 2
154          maxItems: 2
155
156  - if:
157      properties:
158        compatible:
159          contains:
160            enum:
161              - qcom,msm8996-ufshc
162    then:
163      properties:
164        clocks:
165          minItems: 11
166          maxItems: 11
167        clock-names:
168          items:
169            - const: core_clk_src
170            - const: core_clk
171            - const: bus_clk
172            - const: bus_aggr_clk
173            - const: iface_clk
174            - const: core_clk_unipro_src
175            - const: core_clk_unipro
176            - const: core_clk_ice
177            - const: ref_clk
178            - const: tx_lane0_sync_clk
179            - const: rx_lane0_sync_clk
180        reg:
181          minItems: 1
182          maxItems: 1
183
184    # TODO: define clock bindings for qcom,msm8994-ufshc
185
186unevaluatedProperties: false
187
188examples:
189  - |
190    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
191    #include <dt-bindings/clock/qcom,rpmh.h>
192    #include <dt-bindings/gpio/gpio.h>
193    #include <dt-bindings/interconnect/qcom,sm8450.h>
194    #include <dt-bindings/interrupt-controller/arm-gic.h>
195
196    soc {
197        #address-cells = <2>;
198        #size-cells = <2>;
199
200        ufs@1d84000 {
201            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
202                         "jedec,ufs-2.0";
203            reg = <0 0x01d84000 0 0x3000>;
204            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
205            phys = <&ufs_mem_phy_lanes>;
206            phy-names = "ufsphy";
207            lanes-per-direction = <2>;
208            #reset-cells = <1>;
209            resets = <&gcc GCC_UFS_PHY_BCR>;
210            reset-names = "rst";
211            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
212
213            vcc-supply = <&vreg_l7b_2p5>;
214            vcc-max-microamp = <1100000>;
215            vccq-supply = <&vreg_l9b_1p2>;
216            vccq-max-microamp = <1200000>;
217
218            power-domains = <&gcc UFS_PHY_GDSC>;
219            iommus = <&apps_smmu 0xe0 0x0>;
220            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
221                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
222            interconnect-names = "ufs-ddr", "cpu-ufs";
223
224            clock-names = "core_clk",
225                          "bus_aggr_clk",
226                          "iface_clk",
227                          "core_clk_unipro",
228                          "ref_clk",
229                          "tx_lane0_sync_clk",
230                          "rx_lane0_sync_clk",
231                          "rx_lane1_sync_clk";
232            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
233                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
234                     <&gcc GCC_UFS_PHY_AHB_CLK>,
235                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
236                     <&rpmhcc RPMH_CXO_CLK>,
237                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
238                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
239                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
240            freq-table-hz = <75000000 300000000>,
241                            <0 0>,
242                            <0 0>,
243                            <75000000 300000000>,
244                            <75000000 300000000>,
245                            <0 0>,
246                            <0 0>,
247                            <0 0>;
248        };
249    };
250