1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sdm845-ufshc
30          - qcom,sm8150-ufshc
31          - qcom,sm8250-ufshc
32          - qcom,sm8350-ufshc
33          - qcom,sm8450-ufshc
34      - const: qcom,ufshc
35      - const: jedec,ufs-2.0
36
37  clocks:
38    minItems: 8
39    maxItems: 11
40
41  clock-names:
42    minItems: 8
43    maxItems: 11
44
45  interconnects:
46    minItems: 2
47    maxItems: 2
48
49  interconnect-names:
50    items:
51      - const: ufs-ddr
52      - const: cpu-ufs
53
54  iommus:
55    minItems: 1
56    maxItems: 2
57
58  phys:
59    maxItems: 1
60
61  phy-names:
62    items:
63      - const: ufsphy
64
65  power-domains:
66    maxItems: 1
67
68  reg:
69    minItems: 1
70    maxItems: 2
71
72  resets:
73    maxItems: 1
74
75  '#reset-cells':
76    const: 1
77
78  reset-names:
79    items:
80      - const: rst
81
82  reset-gpios:
83    maxItems: 1
84    description:
85      GPIO connected to the RESET pin of the UFS memory device.
86
87required:
88  - compatible
89  - reg
90
91allOf:
92  - $ref: ufs-common.yaml
93
94  - if:
95      properties:
96        compatible:
97          contains:
98            enum:
99              - qcom,msm8998-ufshc
100              - qcom,sm8250-ufshc
101              - qcom,sm8350-ufshc
102              - qcom,sm8450-ufshc
103    then:
104      properties:
105        clocks:
106          minItems: 8
107          maxItems: 8
108        clock-names:
109          items:
110            - const: core_clk
111            - const: bus_aggr_clk
112            - const: iface_clk
113            - const: core_clk_unipro
114            - const: ref_clk
115            - const: tx_lane0_sync_clk
116            - const: rx_lane0_sync_clk
117            - const: rx_lane1_sync_clk
118        reg:
119          minItems: 1
120          maxItems: 1
121
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - qcom,sdm845-ufshc
128              - qcom,sm8150-ufshc
129    then:
130      properties:
131        clocks:
132          minItems: 9
133          maxItems: 9
134        clock-names:
135          items:
136            - const: core_clk
137            - const: bus_aggr_clk
138            - const: iface_clk
139            - const: core_clk_unipro
140            - const: ref_clk
141            - const: tx_lane0_sync_clk
142            - const: rx_lane0_sync_clk
143            - const: rx_lane1_sync_clk
144            - const: ice_core_clk
145        reg:
146          minItems: 2
147          maxItems: 2
148
149  - if:
150      properties:
151        compatible:
152          contains:
153            enum:
154              - qcom,msm8996-ufshc
155    then:
156      properties:
157        clocks:
158          minItems: 11
159          maxItems: 11
160        clock-names:
161          items:
162            - const: core_clk_src
163            - const: core_clk
164            - const: bus_clk
165            - const: bus_aggr_clk
166            - const: iface_clk
167            - const: core_clk_unipro_src
168            - const: core_clk_unipro
169            - const: core_clk_ice
170            - const: ref_clk
171            - const: tx_lane0_sync_clk
172            - const: rx_lane0_sync_clk
173        reg:
174          minItems: 1
175          maxItems: 1
176
177    # TODO: define clock bindings for qcom,msm8994-ufshc
178
179unevaluatedProperties: false
180
181examples:
182  - |
183    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
184    #include <dt-bindings/clock/qcom,rpmh.h>
185    #include <dt-bindings/gpio/gpio.h>
186    #include <dt-bindings/interconnect/qcom,sm8450.h>
187    #include <dt-bindings/interrupt-controller/arm-gic.h>
188
189    soc {
190        #address-cells = <2>;
191        #size-cells = <2>;
192
193        ufs@1d84000 {
194            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
195                         "jedec,ufs-2.0";
196            reg = <0 0x01d84000 0 0x3000>;
197            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
198            phys = <&ufs_mem_phy_lanes>;
199            phy-names = "ufsphy";
200            lanes-per-direction = <2>;
201            #reset-cells = <1>;
202            resets = <&gcc GCC_UFS_PHY_BCR>;
203            reset-names = "rst";
204            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
205
206            vcc-supply = <&vreg_l7b_2p5>;
207            vcc-max-microamp = <1100000>;
208            vccq-supply = <&vreg_l9b_1p2>;
209            vccq-max-microamp = <1200000>;
210
211            power-domains = <&gcc UFS_PHY_GDSC>;
212            iommus = <&apps_smmu 0xe0 0x0>;
213            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
214                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
215            interconnect-names = "ufs-ddr", "cpu-ufs";
216
217            clock-names = "core_clk",
218                          "bus_aggr_clk",
219                          "iface_clk",
220                          "core_clk_unipro",
221                          "ref_clk",
222                          "tx_lane0_sync_clk",
223                          "rx_lane0_sync_clk",
224                          "rx_lane1_sync_clk";
225            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
226                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
227                     <&gcc GCC_UFS_PHY_AHB_CLK>,
228                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
229                     <&rpmhcc RPMH_CXO_CLK>,
230                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
231                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
232                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
233            freq-table-hz = <75000000 300000000>,
234                            <0 0>,
235                            <0 0>,
236                            <75000000 300000000>,
237                            <75000000 300000000>,
238                            <0 0>,
239                            <0 0>,
240                            <0 0>;
241        };
242    };
243