1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sa8775p-ufshc
30          - qcom,sc8280xp-ufshc
31          - qcom,sdm845-ufshc
32          - qcom,sm6115-ufshc
33          - qcom,sm6350-ufshc
34          - qcom,sm8150-ufshc
35          - qcom,sm8250-ufshc
36          - qcom,sm8350-ufshc
37          - qcom,sm8450-ufshc
38          - qcom,sm8550-ufshc
39      - const: qcom,ufshc
40      - const: jedec,ufs-2.0
41
42  clocks:
43    minItems: 8
44    maxItems: 11
45
46  clock-names:
47    minItems: 8
48    maxItems: 11
49
50  dma-coherent: true
51
52  interconnects:
53    minItems: 2
54    maxItems: 2
55
56  interconnect-names:
57    items:
58      - const: ufs-ddr
59      - const: cpu-ufs
60
61  iommus:
62    minItems: 1
63    maxItems: 2
64
65  phys:
66    maxItems: 1
67
68  phy-names:
69    items:
70      - const: ufsphy
71
72  power-domains:
73    maxItems: 1
74
75  qcom,ice:
76    $ref: /schemas/types.yaml#/definitions/phandle
77    description: phandle to the Inline Crypto Engine node
78
79  reg:
80    minItems: 1
81    maxItems: 2
82
83  reg-names:
84    items:
85      - const: std
86      - const: ice
87
88  required-opps:
89    maxItems: 1
90
91  resets:
92    maxItems: 1
93
94  '#reset-cells':
95    const: 1
96
97  reset-names:
98    items:
99      - const: rst
100
101  reset-gpios:
102    maxItems: 1
103    description:
104      GPIO connected to the RESET pin of the UFS memory device.
105
106required:
107  - compatible
108  - reg
109
110allOf:
111  - $ref: ufs-common.yaml
112
113  - if:
114      properties:
115        compatible:
116          contains:
117            enum:
118              - qcom,msm8998-ufshc
119              - qcom,sa8775p-ufshc
120              - qcom,sc8280xp-ufshc
121              - qcom,sm8250-ufshc
122              - qcom,sm8350-ufshc
123              - qcom,sm8450-ufshc
124              - qcom,sm8550-ufshc
125    then:
126      properties:
127        clocks:
128          minItems: 8
129          maxItems: 8
130        clock-names:
131          items:
132            - const: core_clk
133            - const: bus_aggr_clk
134            - const: iface_clk
135            - const: core_clk_unipro
136            - const: ref_clk
137            - const: tx_lane0_sync_clk
138            - const: rx_lane0_sync_clk
139            - const: rx_lane1_sync_clk
140        reg:
141          minItems: 1
142          maxItems: 1
143        reg-names:
144          maxItems: 1
145
146  - if:
147      properties:
148        compatible:
149          contains:
150            enum:
151              - qcom,sdm845-ufshc
152              - qcom,sm6350-ufshc
153              - qcom,sm8150-ufshc
154    then:
155      properties:
156        clocks:
157          minItems: 9
158          maxItems: 9
159        clock-names:
160          items:
161            - const: core_clk
162            - const: bus_aggr_clk
163            - const: iface_clk
164            - const: core_clk_unipro
165            - const: ref_clk
166            - const: tx_lane0_sync_clk
167            - const: rx_lane0_sync_clk
168            - const: rx_lane1_sync_clk
169            - const: ice_core_clk
170        reg:
171          minItems: 2
172          maxItems: 2
173        reg-names:
174          minItems: 2
175      required:
176        - reg-names
177
178  - if:
179      properties:
180        compatible:
181          contains:
182            enum:
183              - qcom,msm8996-ufshc
184    then:
185      properties:
186        clocks:
187          minItems: 11
188          maxItems: 11
189        clock-names:
190          items:
191            - const: core_clk_src
192            - const: core_clk
193            - const: bus_clk
194            - const: bus_aggr_clk
195            - const: iface_clk
196            - const: core_clk_unipro_src
197            - const: core_clk_unipro
198            - const: core_clk_ice
199            - const: ref_clk
200            - const: tx_lane0_sync_clk
201            - const: rx_lane0_sync_clk
202        reg:
203          minItems: 1
204          maxItems: 1
205        reg-names:
206          maxItems: 1
207
208  - if:
209      properties:
210        compatible:
211          contains:
212            enum:
213              - qcom,sm6115-ufshc
214    then:
215      properties:
216        clocks:
217          minItems: 8
218          maxItems: 8
219        clock-names:
220          items:
221            - const: core_clk
222            - const: bus_aggr_clk
223            - const: iface_clk
224            - const: core_clk_unipro
225            - const: ref_clk
226            - const: tx_lane0_sync_clk
227            - const: rx_lane0_sync_clk
228            - const: ice_core_clk
229        reg:
230          minItems: 2
231          maxItems: 2
232        reg-names:
233          minItems: 2
234      required:
235        - reg-names
236
237    # TODO: define clock bindings for qcom,msm8994-ufshc
238
239  - if:
240      required:
241        - qcom,ice
242    then:
243      properties:
244        reg:
245          maxItems: 1
246        clocks:
247          minItems: 8
248          maxItems: 8
249    else:
250      properties:
251        reg:
252          minItems: 1
253          maxItems: 2
254        clocks:
255          minItems: 8
256          maxItems: 11
257
258unevaluatedProperties: false
259
260examples:
261  - |
262    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
263    #include <dt-bindings/clock/qcom,rpmh.h>
264    #include <dt-bindings/gpio/gpio.h>
265    #include <dt-bindings/interconnect/qcom,sm8450.h>
266    #include <dt-bindings/interrupt-controller/arm-gic.h>
267
268    soc {
269        #address-cells = <2>;
270        #size-cells = <2>;
271
272        ufs@1d84000 {
273            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
274                         "jedec,ufs-2.0";
275            reg = <0 0x01d84000 0 0x3000>;
276            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
277            phys = <&ufs_mem_phy_lanes>;
278            phy-names = "ufsphy";
279            lanes-per-direction = <2>;
280            #reset-cells = <1>;
281            resets = <&gcc GCC_UFS_PHY_BCR>;
282            reset-names = "rst";
283            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
284
285            vcc-supply = <&vreg_l7b_2p5>;
286            vcc-max-microamp = <1100000>;
287            vccq-supply = <&vreg_l9b_1p2>;
288            vccq-max-microamp = <1200000>;
289
290            power-domains = <&gcc UFS_PHY_GDSC>;
291            iommus = <&apps_smmu 0xe0 0x0>;
292            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
293                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
294            interconnect-names = "ufs-ddr", "cpu-ufs";
295
296            clock-names = "core_clk",
297                          "bus_aggr_clk",
298                          "iface_clk",
299                          "core_clk_unipro",
300                          "ref_clk",
301                          "tx_lane0_sync_clk",
302                          "rx_lane0_sync_clk",
303                          "rx_lane1_sync_clk";
304            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
305                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
306                     <&gcc GCC_UFS_PHY_AHB_CLK>,
307                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
308                     <&rpmhcc RPMH_CXO_CLK>,
309                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
310                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
311                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
312            freq-table-hz = <75000000 300000000>,
313                            <0 0>,
314                            <0 0>,
315                            <75000000 300000000>,
316                            <75000000 300000000>,
317                            <0 0>,
318                            <0 0>,
319                            <0 0>;
320            qcom,ice = <&ice>;
321        };
322    };
323