1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sa8775p-ufshc
30          - qcom,sc8280xp-ufshc
31          - qcom,sdm845-ufshc
32          - qcom,sm6350-ufshc
33          - qcom,sm8150-ufshc
34          - qcom,sm8250-ufshc
35          - qcom,sm8350-ufshc
36          - qcom,sm8450-ufshc
37          - qcom,sm8550-ufshc
38      - const: qcom,ufshc
39      - const: jedec,ufs-2.0
40
41  clocks:
42    minItems: 8
43    maxItems: 11
44
45  clock-names:
46    minItems: 8
47    maxItems: 11
48
49  dma-coherent: true
50
51  interconnects:
52    minItems: 2
53    maxItems: 2
54
55  interconnect-names:
56    items:
57      - const: ufs-ddr
58      - const: cpu-ufs
59
60  iommus:
61    minItems: 1
62    maxItems: 2
63
64  phys:
65    maxItems: 1
66
67  phy-names:
68    items:
69      - const: ufsphy
70
71  power-domains:
72    maxItems: 1
73
74  reg:
75    minItems: 1
76    maxItems: 2
77
78  required-opps:
79    maxItems: 1
80
81  resets:
82    maxItems: 1
83
84  '#reset-cells':
85    const: 1
86
87  reset-names:
88    items:
89      - const: rst
90
91  reset-gpios:
92    maxItems: 1
93    description:
94      GPIO connected to the RESET pin of the UFS memory device.
95
96required:
97  - compatible
98  - reg
99
100allOf:
101  - $ref: ufs-common.yaml
102
103  - if:
104      properties:
105        compatible:
106          contains:
107            enum:
108              - qcom,msm8998-ufshc
109              - qcom,sa8775p-ufshc
110              - qcom,sc8280xp-ufshc
111              - qcom,sm8250-ufshc
112              - qcom,sm8350-ufshc
113              - qcom,sm8450-ufshc
114              - qcom,sm8550-ufshc
115    then:
116      properties:
117        clocks:
118          minItems: 8
119          maxItems: 8
120        clock-names:
121          items:
122            - const: core_clk
123            - const: bus_aggr_clk
124            - const: iface_clk
125            - const: core_clk_unipro
126            - const: ref_clk
127            - const: tx_lane0_sync_clk
128            - const: rx_lane0_sync_clk
129            - const: rx_lane1_sync_clk
130        reg:
131          minItems: 1
132          maxItems: 1
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            enum:
139              - qcom,sdm845-ufshc
140              - qcom,sm6350-ufshc
141              - qcom,sm8150-ufshc
142    then:
143      properties:
144        clocks:
145          minItems: 9
146          maxItems: 9
147        clock-names:
148          items:
149            - const: core_clk
150            - const: bus_aggr_clk
151            - const: iface_clk
152            - const: core_clk_unipro
153            - const: ref_clk
154            - const: tx_lane0_sync_clk
155            - const: rx_lane0_sync_clk
156            - const: rx_lane1_sync_clk
157            - const: ice_core_clk
158        reg:
159          minItems: 2
160          maxItems: 2
161
162  - if:
163      properties:
164        compatible:
165          contains:
166            enum:
167              - qcom,msm8996-ufshc
168    then:
169      properties:
170        clocks:
171          minItems: 11
172          maxItems: 11
173        clock-names:
174          items:
175            - const: core_clk_src
176            - const: core_clk
177            - const: bus_clk
178            - const: bus_aggr_clk
179            - const: iface_clk
180            - const: core_clk_unipro_src
181            - const: core_clk_unipro
182            - const: core_clk_ice
183            - const: ref_clk
184            - const: tx_lane0_sync_clk
185            - const: rx_lane0_sync_clk
186        reg:
187          minItems: 1
188          maxItems: 1
189
190    # TODO: define clock bindings for qcom,msm8994-ufshc
191
192unevaluatedProperties: false
193
194examples:
195  - |
196    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
197    #include <dt-bindings/clock/qcom,rpmh.h>
198    #include <dt-bindings/gpio/gpio.h>
199    #include <dt-bindings/interconnect/qcom,sm8450.h>
200    #include <dt-bindings/interrupt-controller/arm-gic.h>
201
202    soc {
203        #address-cells = <2>;
204        #size-cells = <2>;
205
206        ufs@1d84000 {
207            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
208                         "jedec,ufs-2.0";
209            reg = <0 0x01d84000 0 0x3000>;
210            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
211            phys = <&ufs_mem_phy_lanes>;
212            phy-names = "ufsphy";
213            lanes-per-direction = <2>;
214            #reset-cells = <1>;
215            resets = <&gcc GCC_UFS_PHY_BCR>;
216            reset-names = "rst";
217            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
218
219            vcc-supply = <&vreg_l7b_2p5>;
220            vcc-max-microamp = <1100000>;
221            vccq-supply = <&vreg_l9b_1p2>;
222            vccq-max-microamp = <1200000>;
223
224            power-domains = <&gcc UFS_PHY_GDSC>;
225            iommus = <&apps_smmu 0xe0 0x0>;
226            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
227                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
228            interconnect-names = "ufs-ddr", "cpu-ufs";
229
230            clock-names = "core_clk",
231                          "bus_aggr_clk",
232                          "iface_clk",
233                          "core_clk_unipro",
234                          "ref_clk",
235                          "tx_lane0_sync_clk",
236                          "rx_lane0_sync_clk",
237                          "rx_lane1_sync_clk";
238            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
239                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
240                     <&gcc GCC_UFS_PHY_AHB_CLK>,
241                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
242                     <&rpmhcc RPMH_CXO_CLK>,
243                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
244                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
245                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
246            freq-table-hz = <75000000 300000000>,
247                            <0 0>,
248                            <0 0>,
249                            <75000000 300000000>,
250                            <75000000 300000000>,
251                            <0 0>,
252                            <0 0>,
253                            <0 0>;
254        };
255    };
256