xref: /openbmc/linux/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml (revision d0672fa4931dcb9d9d53002e855f25dd7507a300) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Tegra on chip generic hardware timestamping engine (HTE) provider
8
9maintainers:
10  - Dipen Patel <dipenp@nvidia.com>
11
12description:
13  Tegra SoC has two instances of generic hardware timestamping engines (GTE)
14  known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
15  IRQ lines for the state change respectively, upon detection it will record
16  timestamp (taken from system counter) in its internal hardware FIFO. It has
17  a bitmap array arranged in 32bit slices where each bit represent signal/line
18  to enable or disable for the hardware timestamping. The GTE GPIO monitors
19  GPIO lines from the AON (always on) GPIO controller.
20
21properties:
22  compatible:
23    enum:
24      - nvidia,tegra194-gte-aon
25      - nvidia,tegra194-gte-lic
26      - nvidia,tegra234-gte-aon
27      - nvidia,tegra234-gte-lic
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  nvidia,int-threshold:
36    $ref: /schemas/types.yaml#/definitions/uint32
37    description:
38      HTE device generates its interrupt based on this u32 FIFO threshold
39      value. The recommended value is 1.
40    minimum: 1
41    maximum: 256
42
43  nvidia,slices:
44    $ref: /schemas/types.yaml#/definitions/uint32
45    description:
46      HTE lines are arranged in 32 bit slice where each bit represents different
47      line/signal that it can enable/configure for the timestamp. It is u32
48      property and the value depends on the HTE instance in the chip.
49    enum: [3, 11, 17]
50
51  nvidia,gpio-controller:
52    $ref: /schemas/types.yaml#/definitions/phandle
53    description:
54      The phandle to AON gpio controller instance. This is required to handle
55      namespace conversion between GPIO and GTE.
56
57  '#timestamp-cells':
58    description:
59      This represents number of line id arguments as specified by the
60      consumers. For the GTE IRQ, this is IRQ number as mentioned in the
61      SoC technical reference manual. For the GTE GPIO, its value is same as
62      mentioned in the nvidia GPIO device tree binding document.
63    const: 1
64
65required:
66  - compatible
67  - reg
68  - interrupts
69  - nvidia,slices
70  - "#timestamp-cells"
71
72allOf:
73  - if:
74      properties:
75        compatible:
76          contains:
77            enum:
78              - nvidia,tegra194-gte-aon
79              - nvidia,tegra234-gte-aon
80    then:
81      properties:
82        nvidia,slices:
83          const: 3
84
85  - if:
86      properties:
87        compatible:
88          contains:
89            enum:
90              - nvidia,tegra194-gte-lic
91    then:
92      properties:
93        nvidia,slices:
94          const: 11
95
96  - if:
97      properties:
98        compatible:
99          contains:
100            enum:
101              - nvidia,tegra234-gte-lic
102    then:
103      properties:
104        nvidia,slices:
105          const: 17
106
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - nvidia,tegra234-gte-aon
113    then:
114      required:
115        - nvidia,gpio-controller
116
117additionalProperties: false
118
119examples:
120  - |
121    tegra_hte_aon: timestamp@c1e0000 {
122              compatible = "nvidia,tegra194-gte-aon";
123              reg = <0xc1e0000 0x10000>;
124              interrupts = <0 13 0x4>;
125              nvidia,int-threshold = <1>;
126              nvidia,slices = <3>;
127              #timestamp-cells = <1>;
128    };
129
130  - |
131    tegra_hte_lic: timestamp@3aa0000 {
132              compatible = "nvidia,tegra194-gte-lic";
133              reg = <0x3aa0000 0x10000>;
134              interrupts = <0 11 0x4>;
135              nvidia,int-threshold = <1>;
136              nvidia,slices = <11>;
137              #timestamp-cells = <1>;
138    };
139
140...
141