1*af583852SDipen Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*af583852SDipen Patel%YAML 1.2 3*af583852SDipen Patel--- 4*af583852SDipen Patel$id: http://devicetree.org/schemas/hte/nvidia,tegra194-hte.yaml# 5*af583852SDipen Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*af583852SDipen Patel 7*af583852SDipen Pateltitle: Tegra194 on chip generic hardware timestamping engine (HTE) 8*af583852SDipen Patel 9*af583852SDipen Patelmaintainers: 10*af583852SDipen Patel - Dipen Patel <dipenp@nvidia.com> 11*af583852SDipen Patel 12*af583852SDipen Pateldescription: 13*af583852SDipen Patel Tegra SoC has two instances of generic hardware timestamping engines (GTE) 14*af583852SDipen Patel known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip 15*af583852SDipen Patel IRQ lines for the state change respectively, upon detection it will record 16*af583852SDipen Patel timestamp (taken from system counter) in its internal hardware FIFO. It has 17*af583852SDipen Patel a bitmap array arranged in 32bit slices where each bit represent signal/line 18*af583852SDipen Patel to enable or disable for the hardware timestamping. The GTE GPIO monitors 19*af583852SDipen Patel GPIO lines from the AON (always on) GPIO controller. 20*af583852SDipen Patel 21*af583852SDipen Patelproperties: 22*af583852SDipen Patel compatible: 23*af583852SDipen Patel enum: 24*af583852SDipen Patel - nvidia,tegra194-gte-aon 25*af583852SDipen Patel - nvidia,tegra194-gte-lic 26*af583852SDipen Patel 27*af583852SDipen Patel reg: 28*af583852SDipen Patel maxItems: 1 29*af583852SDipen Patel 30*af583852SDipen Patel interrupts: 31*af583852SDipen Patel maxItems: 1 32*af583852SDipen Patel 33*af583852SDipen Patel nvidia,int-threshold: 34*af583852SDipen Patel $ref: /schemas/types.yaml#/definitions/uint32 35*af583852SDipen Patel description: 36*af583852SDipen Patel HTE device generates its interrupt based on this u32 FIFO threshold 37*af583852SDipen Patel value. The recommended value is 1. 38*af583852SDipen Patel minimum: 1 39*af583852SDipen Patel maximum: 256 40*af583852SDipen Patel 41*af583852SDipen Patel nvidia,slices: 42*af583852SDipen Patel $ref: /schemas/types.yaml#/definitions/uint32 43*af583852SDipen Patel description: 44*af583852SDipen Patel HTE lines are arranged in 32 bit slice where each bit represents different 45*af583852SDipen Patel line/signal that it can enable/configure for the timestamp. It is u32 46*af583852SDipen Patel property and depends on the HTE instance in the chip. The value 3 is for 47*af583852SDipen Patel GPIO GTE and 11 for IRQ GTE. 48*af583852SDipen Patel enum: [3, 11] 49*af583852SDipen Patel 50*af583852SDipen Patel '#timestamp-cells': 51*af583852SDipen Patel description: 52*af583852SDipen Patel This represents number of line id arguments as specified by the 53*af583852SDipen Patel consumers. For the GTE IRQ, this is IRQ number as mentioned in the 54*af583852SDipen Patel SoC technical reference manual. For the GTE GPIO, its value is same as 55*af583852SDipen Patel mentioned in the nvidia GPIO device tree binding document. 56*af583852SDipen Patel const: 1 57*af583852SDipen Patel 58*af583852SDipen Patelrequired: 59*af583852SDipen Patel - compatible 60*af583852SDipen Patel - reg 61*af583852SDipen Patel - interrupts 62*af583852SDipen Patel - nvidia,slices 63*af583852SDipen Patel - "#timestamp-cells" 64*af583852SDipen Patel 65*af583852SDipen PateladditionalProperties: false 66*af583852SDipen Patel 67*af583852SDipen Patelexamples: 68*af583852SDipen Patel - | 69*af583852SDipen Patel tegra_hte_aon: timestamp@c1e0000 { 70*af583852SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 71*af583852SDipen Patel reg = <0xc1e0000 0x10000>; 72*af583852SDipen Patel interrupts = <0 13 0x4>; 73*af583852SDipen Patel nvidia,int-threshold = <1>; 74*af583852SDipen Patel nvidia,slices = <3>; 75*af583852SDipen Patel #timestamp-cells = <1>; 76*af583852SDipen Patel }; 77*af583852SDipen Patel 78*af583852SDipen Patel - | 79*af583852SDipen Patel tegra_hte_lic: timestamp@3aa0000 { 80*af583852SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 81*af583852SDipen Patel reg = <0x3aa0000 0x10000>; 82*af583852SDipen Patel interrupts = <0 11 0x4>; 83*af583852SDipen Patel nvidia,int-threshold = <1>; 84*af583852SDipen Patel nvidia,slices = <11>; 85*af583852SDipen Patel #timestamp-cells = <1>; 86*af583852SDipen Patel }; 87*af583852SDipen Patel 88*af583852SDipen Patel... 89