1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24  their implementation lacks a memory-mapped MTIME register, thus not
25  compatible with SiFive ones.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - sifive,fu540-c000-clint
33              - starfive,jh7100-clint
34              - starfive,jh7110-clint
35              - canaan,k210-clint
36          - const: sifive,clint0
37      - items:
38          - enum:
39              - allwinner,sun20i-d1-clint
40          - const: thead,c900-clint
41      - items:
42          - const: sifive,clint0
43          - const: riscv,clint0
44        deprecated: true
45        description: For the QEMU virt machine only
46
47    description:
48      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
49      Supported compatible strings are -
50      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
51      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
52      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
53      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
54      integration tweaks.
55      Please refer to sifive-blocks-ip-versioning.txt for details
56
57  reg:
58    maxItems: 1
59
60  interrupts-extended:
61    minItems: 1
62    maxItems: 4095
63
64additionalProperties: false
65
66required:
67  - compatible
68  - reg
69  - interrupts-extended
70
71examples:
72  - |
73    timer@2000000 {
74      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
75      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
76                            <&cpu2intc 3>, <&cpu2intc 7>,
77                            <&cpu3intc 3>, <&cpu3intc 7>,
78                            <&cpu4intc 3>, <&cpu4intc 7>;
79       reg = <0x2000000 0x10000>;
80    };
81...
82