1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23properties:
24  compatible:
25    items:
26      - const: sifive,fu540-c000-clint
27      - const: sifive,clint0
28
29    description:
30      Should be "sifive,<chip>-clint" and "sifive,clint<version>".
31      Supported compatible strings are -
32      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
33      onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
34      CLINT v0 IP block with no chip integration tweaks.
35      Please refer to sifive-blocks-ip-versioning.txt for details
36
37  reg:
38    maxItems: 1
39
40  interrupts-extended:
41    minItems: 1
42
43additionalProperties: false
44
45required:
46  - compatible
47  - reg
48  - interrupts-extended
49
50examples:
51  - |
52    timer@2000000 {
53      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
54      interrupts-extended = <&cpu1intc 3 &cpu1intc 7
55                             &cpu2intc 3 &cpu2intc 7
56                             &cpu3intc 3 &cpu3intc 7
57                             &cpu4intc 3 &cpu4intc 7>;
58       reg = <0x2000000 0x10000>;
59    };
60...
61