1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas OS Timer (OSTM)
8
9maintainers:
10  - Chris Brandt <chris.brandt@renesas.com>
11  - Geert Uytterhoeven <geert+renesas@glider.be>
12
13description:
14  The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
15  can operate in either interval count down timer or free-running compare match
16  mode.
17
18  Channels are independent from each other.
19
20properties:
21  compatible:
22    items:
23      - enum:
24          - renesas,r7s72100-ostm  # RZ/A1H
25          - renesas,r7s9210-ostm   # RZ/A2M
26          - renesas,r9a07g044-ostm # RZ/G2{L,LC}
27          - renesas,r9a07g054-ostm # RZ/V2L
28      - const: renesas,ostm        # Generic
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  power-domains:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45required:
46  - compatible
47  - reg
48  - interrupts
49  - clocks
50  - power-domains
51
52if:
53  properties:
54    compatible:
55      contains:
56        enum:
57          - renesas,r9a07g044-ostm
58          - renesas,r9a07g054-ostm
59then:
60  required:
61    - resets
62
63additionalProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/clock/r7s72100-clock.h>
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69    ostm0: timer@fcfec000 {
70            compatible = "renesas,r7s72100-ostm", "renesas,ostm";
71            reg = <0xfcfec000 0x30>;
72            interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
73            clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
74            power-domains = <&cpg_clocks>;
75    };
76