1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/timer/renesas,cmt.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas Compare Match Timer (CMT) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 12 13description: 14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock 15 inputs and programmable compare match. 16 17 Channels share hardware resources but their counter and compare match values 18 are independent. A particular CMT instance can implement only a subset of the 19 channels supported by the CMT model. Channel indices represent the hardware 20 position of the channel in the CMT and don't match the channel numbers in the 21 datasheets. 22 23properties: 24 compatible: 25 oneOf: 26 - items: 27 - enum: 28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1 29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1 30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1 31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1 32 - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1 33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5 34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5 35 - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5 36 - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5 37 - renesas,sh73a0-cmt4 # 32-bit CMT4 on SH-Mobile AG5 38 39 - items: 40 - enum: 41 - renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6 42 - renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H 43 - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M 44 - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N 45 - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E 46 - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C 47 - renesas,r8a7790-cmt0 # 32-bit CMT0 on R-Car H2 48 - renesas,r8a7791-cmt0 # 32-bit CMT0 on R-Car M2-W 49 - renesas,r8a7792-cmt0 # 32-bit CMT0 on R-Car V2H 50 - renesas,r8a7793-cmt0 # 32-bit CMT0 on R-Car M2-N 51 - renesas,r8a7794-cmt0 # 32-bit CMT0 on R-Car E2 52 - const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1 53 54 - items: 55 - enum: 56 - renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6 57 - renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H 58 - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M 59 - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N 60 - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E 61 - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C 62 - renesas,r8a7790-cmt1 # 48-bit CMT1 on R-Car H2 63 - renesas,r8a7791-cmt1 # 48-bit CMT1 on R-Car M2-W 64 - renesas,r8a7792-cmt1 # 48-bit CMT1 on R-Car V2H 65 - renesas,r8a7793-cmt1 # 48-bit CMT1 on R-Car M2-N 66 - renesas,r8a7794-cmt1 # 48-bit CMT1 on R-Car E2 67 - const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1 68 69 - items: 70 - enum: 71 - renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M 72 - renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N 73 - renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E 74 - renesas,r8a774e1-cmt0 # 32-bit CMT0 on RZ/G2H 75 - renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3 76 - renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W 77 - renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N 78 - renesas,r8a77970-cmt0 # 32-bit CMT0 on R-Car V3M 79 - renesas,r8a77980-cmt0 # 32-bit CMT0 on R-Car V3H 80 - renesas,r8a77990-cmt0 # 32-bit CMT0 on R-Car E3 81 - renesas,r8a77995-cmt0 # 32-bit CMT0 on R-Car D3 82 - const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2 83 84 - items: 85 - enum: 86 - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M 87 - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N 88 - renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E 89 - renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H 90 - renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3 91 - renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W 92 - renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N 93 - renesas,r8a77970-cmt1 # 48-bit CMT on R-Car V3M 94 - renesas,r8a77980-cmt1 # 48-bit CMT on R-Car V3H 95 - renesas,r8a77990-cmt1 # 48-bit CMT on R-Car E3 96 - renesas,r8a77995-cmt1 # 48-bit CMT on R-Car D3 97 - const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2 98 99 reg: 100 maxItems: 1 101 102 interrupts: 103 minItems: 1 104 maxItems: 8 105 106 clocks: 107 maxItems: 1 108 109 clock-names: 110 const: fck 111 112 power-domains: 113 maxItems: 1 114 115 resets: 116 maxItems: 1 117 118required: 119 - compatible 120 - reg 121 - interrupts 122 - clocks 123 - clock-names 124 - power-domains 125 126allOf: 127 - if: 128 properties: 129 compatible: 130 contains: 131 enum: 132 - renesas,rcar-gen2-cmt0 133 - renesas,rcar-gen3-cmt0 134 then: 135 properties: 136 interrupts: 137 minItems: 2 138 maxItems: 2 139 140 - if: 141 properties: 142 compatible: 143 contains: 144 enum: 145 - renesas,rcar-gen2-cmt1 146 - renesas,rcar-gen3-cmt1 147 then: 148 properties: 149 interrupts: 150 minItems: 8 151 maxItems: 8 152 153additionalProperties: false 154 155examples: 156 - | 157 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 158 #include <dt-bindings/interrupt-controller/arm-gic.h> 159 #include <dt-bindings/power/r8a7790-sysc.h> 160 cmt0: timer@ffca0000 { 161 compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; 162 reg = <0xffca0000 0x1004>; 163 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&cpg CPG_MOD 124>; 166 clock-names = "fck"; 167 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 168 resets = <&cpg 124>; 169 }; 170 171 cmt1: timer@e6130000 { 172 compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; 173 reg = <0xe6130000 0x1004>; 174 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&cpg CPG_MOD 329>; 183 clock-names = "fck"; 184 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 185 resets = <&cpg 329>; 186 }; 187