198c6bf2aSMatthias BruggerMediatek MT6577, MT6572 and MT6589 Timers 298c6bf2aSMatthias Brugger--------------------------------------- 398c6bf2aSMatthias Brugger 498c6bf2aSMatthias BruggerRequired properties: 569a462b9SMars Cheng- compatible should contain: 669a462b9SMars Cheng * "mediatek,mt6589-timer" for MT6589 compatible timers 769a462b9SMars Cheng * "mediatek,mt6580-timer" for MT6580 compatible timers 869a462b9SMars Cheng * "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580, 969a462b9SMars Cheng MT6577) 1098c6bf2aSMatthias Brugger- reg: Should contain location and length for timers register. 1198c6bf2aSMatthias Brugger- clocks: Clocks driving the timer hardware. This list should include two 1298c6bf2aSMatthias Brugger clocks. The order is system clock and as second clock the RTC clock. 1398c6bf2aSMatthias Brugger 1498c6bf2aSMatthias BruggerExamples: 1598c6bf2aSMatthias Brugger 1698c6bf2aSMatthias Brugger timer@10008000 { 1798c6bf2aSMatthias Brugger compatible = "mediatek,mt6577-timer"; 1898c6bf2aSMatthias Brugger reg = <0x10008000 0x80>; 1998c6bf2aSMatthias Brugger interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; 2098c6bf2aSMatthias Brugger clocks = <&system_clk>, <&rtc_clk>; 2198c6bf2aSMatthias Brugger }; 22