1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright 2020 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/thermal-idle.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Thermal idle cooling device binding 9 10maintainers: 11 - Daniel Lezcano <daniel.lezcano@linaro.org> 12 13description: | 14 The thermal idle cooling device allows the system to passively 15 mitigate the temperature on the device by injecting idle cycles, 16 forcing it to cool down. 17 18 This binding describes the thermal idle node. 19 20properties: 21 $nodename: 22 const: thermal-idle 23 description: | 24 A thermal-idle node describes the idle cooling device properties to 25 cool down efficiently the attached thermal zone. 26 27 '#cooling-cells': 28 const: 2 29 description: | 30 Must be 2, in order to specify minimum and maximum cooling state used in 31 the cooling-maps reference. The first cell is the minimum cooling state 32 and the second cell is the maximum cooling state requested. 33 34 duration-us: 35 description: | 36 The idle duration in microsecond the device should cool down. 37 38 exit-latency-us: 39 description: | 40 The exit latency constraint in microsecond for the injected idle state 41 for the device. It is the latency constraint to apply when selecting an 42 idle state from among all the present ones. 43 44required: 45 - '#cooling-cells' 46 47examples: 48 - | 49 #include <dt-bindings/thermal/thermal.h> 50 51 // Example: Combining idle cooling device on big CPUs with cpufreq cooling device 52 cpus { 53 #address-cells = <2>; 54 #size-cells = <0>; 55 56 /* ... */ 57 58 cpu_b0: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a72"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 capacity-dmips-mhz = <1024>; 64 dynamic-power-coefficient = <436>; 65 #cooling-cells = <2>; /* min followed by max */ 66 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 67 thermal-idle { 68 #cooling-cells = <2>; 69 duration-us = <10000>; 70 exit-latency-us = <500>; 71 }; 72 }; 73 74 cpu_b1: cpu@101 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a72"; 77 reg = <0x0 0x101>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <436>; 81 #cooling-cells = <2>; /* min followed by max */ 82 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 83 thermal-idle { 84 #cooling-cells = <2>; 85 duration-us = <10000>; 86 exit-latency-us = <500>; 87 }; 88 }; 89 90 /* ... */ 91 92 }; 93 94 /* ... */ 95 96 thermal_zones { 97 cpu_thermal: cpu { 98 polling-delay-passive = <100>; 99 polling-delay = <1000>; 100 101 /* ... */ 102 103 trips { 104 cpu_alert0: cpu_alert0 { 105 temperature = <65000>; 106 hysteresis = <2000>; 107 type = "passive"; 108 }; 109 110 cpu_alert1: cpu_alert1 { 111 temperature = <70000>; 112 hysteresis = <2000>; 113 type = "passive"; 114 }; 115 116 cpu_alert2: cpu_alert2 { 117 temperature = <75000>; 118 hysteresis = <2000>; 119 type = "passive"; 120 }; 121 122 cpu_crit: cpu_crit { 123 temperature = <95000>; 124 hysteresis = <2000>; 125 type = "critical"; 126 }; 127 }; 128 129 cooling-maps { 130 map0 { 131 trip = <&cpu_alert1>; 132 cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >, 133 <&{/cpus/cpu@101/thermal-idle} 0 15>; 134 }; 135 136 map1 { 137 trip = <&cpu_alert2>; 138 cooling-device = 139 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 140 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 141 }; 142 }; 143 }; 144 }; 145