1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright 2021 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Qualcomm Limits Management Hardware(LMh) 9 10maintainers: 11 - Thara Gopinath <thara.gopinath@gmail.com> 12 13description: 14 Limits Management Hardware(LMh) is a hardware infrastructure on some 15 Qualcomm SoCs that can enforce temperature and current limits as 16 programmed by software for certain IPs like CPU. 17 18properties: 19 compatible: 20 enum: 21 - qcom,sc8180x-lmh 22 - qcom,sdm845-lmh 23 - qcom,sm8150-lmh 24 25 reg: 26 items: 27 - description: core registers 28 29 interrupts: 30 maxItems: 1 31 32 '#interrupt-cells': 33 const: 1 34 35 interrupt-controller: true 36 37 cpus: 38 description: 39 phandle of the first cpu in the LMh cluster 40 maxItems: 1 41 42 qcom,lmh-temp-arm-millicelsius: 43 description: 44 An integer expressing temperature threshold at which the LMh thermal 45 FSM is engaged. 46 47 qcom,lmh-temp-low-millicelsius: 48 description: 49 An integer expressing temperature threshold at which the state machine 50 will attempt to remove frequency throttling. 51 52 qcom,lmh-temp-high-millicelsius: 53 description: 54 An integer expressing temperature threshold at which the state machine 55 will attempt to throttle the frequency. 56 57required: 58 - compatible 59 - reg 60 - interrupts 61 - '#interrupt-cells' 62 - interrupt-controller 63 - cpus 64 - qcom,lmh-temp-arm-millicelsius 65 - qcom,lmh-temp-low-millicelsius 66 - qcom,lmh-temp-high-millicelsius 67 68additionalProperties: false 69 70examples: 71 - | 72 #include <dt-bindings/interrupt-controller/arm-gic.h> 73 74 lmh@17d70800 { 75 compatible = "qcom,sdm845-lmh"; 76 reg = <0x17d70800 0x400>; 77 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 78 cpus = <&CPU4>; 79 qcom,lmh-temp-arm-millicelsius = <65000>; 80 qcom,lmh-temp-low-millicelsius = <94500>; 81 qcom,lmh-temp-high-millicelsius = <95000>; 82 interrupt-controller; 83 #interrupt-cells = <1>; 84 }; 85